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Showing items 1-10 of 44 (5 Page(s) Totally)
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| 國立交通大學 |
2019-04-02T06:04:32Z |
Thin Film Silicon Solar Cell Fabricated at 100 degrees C by High Density Plasma for Flexible Photovoltaic Application
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Shen, Chang-Hong; Shieh, Jia-Min; Kuo, Hao-Chung; Huang, Jung Y.; Yu, Wen-Chien; Huang, Wen-Hsien; Wang, Chao-Kei; Hsu, Chih-Wei; Lin, Yu-Hsin; Chiu, Hung-Yu; Dai, Bau-Tong; Yang, Fu-Liang |
| 國立交通大學 |
2018-08-21T05:56:39Z |
A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
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Tang, Ying-Tsan; Li, Kai-Shin; Li, Lain-Jong; Li, Ming-Yang; Lin, Chang-Hsien; Chen, Yi-Ju; Chen, Chun-Chi; Su, Chuan-Jung; Wu, Bo-Wei; Wu, Cheng-San; Chen, Min-Cheng; Shieh, Jia-Min; Yeh, Wen-Kuan; Su, Po-Cheng; Wang, Tahui; Yang, Fu-Liang; Hu, Chenming |
| 國立交通大學 |
2018-08-21T05:56:34Z |
Threshold Vacuum Switch (TVS) on 3D-Stackable and 4F(2) Cross-Point Bipolar and Unipolar Resistive Random Access Memory
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Ho, ChiaHua; Huang, Hsin-Hau; Lee, Ming-Taou; Hsu, Cho-Lun; Lai, Tung-Yen; Chiu, Wen-Cheng; Lee, Meiyi; Chou, Tong-Huan; Yang, Ivy; Chen, Min-Cheng; Wu, Cheng-San; Chiang, Kuang-Hao; Yao, Yong-Der; Hu, Chenming; Yang, Fu-Liang |
| 國立交通大學 |
2018-08-21T05:56:34Z |
3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
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Lien, Yu-Chung; Shieh, Jia-Min; Huang, Wen-Hsien; Hsieh, Wei-Shang; Tu, Cheng-Hui; Wang, Chieh; Shen, Chang-Hong; Chou, Tung-Huan; Chen, Min-Cheng; Huang, Jung Y.; Pan, Ci-Ling; Lai, Yin-Chieh; Hu, Chenming; Yang, Fu-Liang |
| 國立交通大學 |
2018-08-21T05:56:33Z |
CIGS solar cell integrated with high mobility microcrystalline Si TFTs on 30X40 cm(2) glass panels for self powered electronics
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Shen, Chang-Hong; Shieh, Jia-Min; Wu, Tsung-Ta; Huang, Jung Y.; Huang, Che-Hsuan; Huang, Yu-Hsiang; Lu, Tien-Chang; Dai, Bau-Tong; Hu, Chenming; Yang, Fu-Liang |
| 國立交通大學 |
2017-04-21T06:50:15Z |
MOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 Availability
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Li, Kai-Shin; Wu, Bo-Wei; Li, Lain-Jong; Li, Ming-Yang; Cheng, Chia-Chin Kevin; Hsu, Cho-Lun; Lin, Chang-Hsien; Chen, Yi-Ju; Chen, Chun-Chi; Wu, Chien-Ting; Chen, Min-Cheng; Shieh, Jia-Min; Yeh, Wen-Kuan; Chueh, Yu-Lun; Yang, Fu-Liang; Hu, Chenming |
| 國立交通大學 |
2017-04-21T06:50:09Z |
Silicide Barrier Engineering Induced Random Telegraph Noise in 1Xnm CMOS Contacts
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Chen, Min-Cheng; Lin, Chia-Yi; Chen, Bo-Yuan; Lin, Chang-Hsien; Huang, Guo-Wei; Huang, Chien-Chao; Ho, ChiaHua; Wang, Tahui; Hu, Chenming; Yang, Fu-Liang |
| 國立交通大學 |
2017-04-21T06:50:08Z |
Near-omni-directional sub-micron Silica light-trapping monolayer for amorphous Si photovoltaic devices
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Huang, Wen-Hsien; Shieh, Jia-Min; Shen, Chang-Hong; Huang, Jung Y.; Kuo, Hao-Chung; Pan, Fu-Ming; Hsu, Chih-Wei; Dai, Bau-Tong; Lee, Ching-Ting; Pan, Ci-Ling; Yang, Fu-Liang |
| 國立交通大學 |
2017-04-21T06:49:53Z |
Novel 140 degrees C Hybrid Thin Film Solar Cell/Transistor Technology with 9.6% Conversion Efficiency and 1.1 cm2/V-s Electron Mobility for Low-Temperature Substrates
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Shen, Chang-Hong; Shieh, Jia-Min; Kuo, Hao-Chung; Huang, Jung Y.; Huang, Wen-Hsien; Hsu, Chih-Wei; Lin, Yu-Hsin; Chiu, Hung-Yu; Jhan, Huang-Yan; Dai, Bau-Tong; Lee, Ching-Ting; Pan, Ci-Ling; Hu, Chenming; Yang, Fu-Liang |
| 國立交通大學 |
2017-04-21T06:49:48Z |
Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM
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Shen, Chang-Hong; Shieh, Jia-Min; Wu, Tsung-Ta; Huang, Wen-Hsien; Yang, Chih-Chao; Wan, Chih-Jen; Lin, Chein-Din; Wang, Hsing-Hsiang; Chen, Bo-Yuan; Huang, Guo-Wei; Lien, Yu-Chung; Wong, Simon; Wang, Chieh; Lai, Yin-Chieh; Chen, Chien-Fu; Chang, Meng-Fan; Hu, Chenming; Yang, Fu-Liang |
Showing items 1-10 of 44 (5 Page(s) Totally)
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