|
English
|
正體中文
|
简体中文
|
总笔数 :2823486
|
|
造访人次 :
30315888
在线人数 :
833
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
"yang wei bin"的相关文件
显示项目 1-10 / 79 (共8页)
1 2 3 4 5 6 7 8 > >>
每页显示[10|25|50]项目
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2023-10-21 |
A Multi-Stage Dual Mode Digital LDO with Fast Transient Response and Adaptive Frequency
|
Yang, Wei-Bin;Chu, Li-Lun;Chen, Tse-Yu;Lin, Cheng-Kai;Roy, Diptendu Sinha |
| 淡江大學 |
2023-09-05 |
High-Efficiency and Wide-Load Current Range LDO Regulator with Dynamic Loop Gain Control Technique
|
Chiu, Yu-Chun;Lo, Yu-Lung;Lin, Chia-Wen;Yang, Wei-Bin |
| 淡江大學 |
2022-09 |
A Programmable Multiple Frequencies Clock Generator with Process and Temperature Compensation Circuit for System on Chip Design
|
Yang, Wei-Bin;Chang, Kuo-Ning;Yeh, Lu-Chun |
| 淡江大學 |
2021-12-03 |
Asynchronous Digital Low-Dropout Regulator with Dual Adjustment Mode in Ultra-Low Voltage Input
|
Yang, Wei-Bin;Sun, Chi-Hsuan;Roy, Diptendu Sinha;Chen, Yi-Mei |
| 淡江大學 |
2020-03-06 |
A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications
|
Yang, Wei-Bin;Wang, Hsi-Hua;Chang, Hsin-I;Lo, Yu-Lung |
| 淡江大學 |
2019-05-07 |
A Sensitivity-Power Efficiency Adjustable Wake-Up Receiver with Injection-Locked Oscillator Calibration
|
Shih, Horng-Yuan;Chang, Yu-Chuan;Chen, Chieh-Chih;Yang, Wei-Bin |
| 淡江大學 |
2019-02-22 |
A Fast Transient Response and High Current Efficiency Output-Capacitorless Low Dropout Regulator for Low-Power SoC Applications
|
Yang, Wei-Bin;Li, Yu-Hsin;Yu, Cheng-Yang;Lo, Yu-Lung |
显示项目 1-10 / 79 (共8页)
1 2 3 4 5 6 7 8 > >>
每页显示[10|25|50]项目
|
