|
"yang wei bin"的相關文件
顯示項目 1-25 / 79 (共4頁)
1 2 3 4 > >>
每頁顯示[10|25|50]項目
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2023-10-21 |
A Multi-Stage Dual Mode Digital LDO with Fast Transient Response and Adaptive Frequency
|
Yang, Wei-Bin;Chu, Li-Lun;Chen, Tse-Yu;Lin, Cheng-Kai;Roy, Diptendu Sinha |
| 淡江大學 |
2023-09-05 |
High-Efficiency and Wide-Load Current Range LDO Regulator with Dynamic Loop Gain Control Technique
|
Chiu, Yu-Chun;Lo, Yu-Lung;Lin, Chia-Wen;Yang, Wei-Bin |
| 淡江大學 |
2022-09 |
A Programmable Multiple Frequencies Clock Generator with Process and Temperature Compensation Circuit for System on Chip Design
|
Yang, Wei-Bin;Chang, Kuo-Ning;Yeh, Lu-Chun |
| 淡江大學 |
2021-12-03 |
Asynchronous Digital Low-Dropout Regulator with Dual Adjustment Mode in Ultra-Low Voltage Input
|
Yang, Wei-Bin;Sun, Chi-Hsuan;Roy, Diptendu Sinha;Chen, Yi-Mei |
| 淡江大學 |
2020-03-06 |
A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications
|
Yang, Wei-Bin;Wang, Hsi-Hua;Chang, Hsin-I;Lo, Yu-Lung |
| 淡江大學 |
2019-05-07 |
A Sensitivity-Power Efficiency Adjustable Wake-Up Receiver with Injection-Locked Oscillator Calibration
|
Shih, Horng-Yuan;Chang, Yu-Chuan;Chen, Chieh-Chih;Yang, Wei-Bin |
| 淡江大學 |
2019-02-22 |
A Fast Transient Response and High Current Efficiency Output-Capacitorless Low Dropout Regulator for Low-Power SoC Applications
|
Yang, Wei-Bin;Li, Yu-Hsin;Yu, Cheng-Yang;Lo, Yu-Lung |
| 淡江大學 |
2018 |
A current-controlled oscillator with temperature, voltage, and process compensation
|
Yang, Wei-Bin;Chiang, Jen-Shiun;Cheng, Ching-Tsan;Wang, Chi-Hsiung;Shih, Horng-Yuan;Syu, Jia-Liang;Chen, Cing-Huan;Lo, Yu-Lung |
| 淡江大學 |
2017年10月 |
All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application
|
Tsai, Chih-Wei;Lo, Yu-Lung;Chang, Chia-Chen;Liu, Han-Ying;Yang, Wei-Bin;Cheng, Kuo-Hsing |
| 淡江大學 |
2017年10月 |
A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4
|
Lo, Yu-Lung;Yang, Wei-Bin;Wang, Han-Hsien;Chen, Cing-Huan;Huang, Zi-Ang |
| 淡江大學 |
2017年10月 |
Wide‑range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9‑V supply voltage
|
Yang, Wei-Bin;Lo, Yu-Lung;Chang, Kuo-Ning;Lin, Yu-Yao |
| 淡江大學 |
2017-05-13 |
A Multi-Rate QPSK Transmitter for Wearable or Implantable Biomedical Devices
|
Yang, Pei-Ting;Shih, Horng-Yuan;Yang, Cheng-Wei;Shih, Jung-Tai;Chang, Yu-Chuan;Yang, Wei-Bin |
| 淡江大學 |
2015/09/13 |
A 1.8-V Temperature Coefficient is 4.36-ppm/°C Bandgap Reference Current with Process Calibration
|
Yang, Wei-Bin |
| 淡江大學 |
2015/09/13 |
Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in 90nm Process
|
Yang, Wei-Bin |
| 淡江大學 |
2015/09/13 |
A 25MHz Crystal Less Clock Generator with Background Calibration Against Process and Temperature Variation
|
Yang, Wei-Bin |
| 淡江大學 |
2015/09/13 |
A new multiple frequency out of DLL with Glitch Elimination and Phase Interpolator
|
Yang, Wei-Bin |
| 淡江大學 |
2015/09/13 |
Wide Range CMOS Reference Clock Generator with Dynamic Duty Cycle Scaling Mechanism in 0.9V Supply Voltage
|
Yang, Wei-Bin |
| 淡江大學 |
2015/09/13 |
A fast-lock and low-power Delay-Locked-Loop applied for DDR4
|
Yang, Wei-Bin |
| 淡江大學 |
2015/09/13 |
A Transient Enhanced LDO with Current Buffer for SoC Application
|
Yang, Wei-Bin |
| 淡江大學 |
2015/09/13 |
A Current-Controlled Oscillator with Temperature, Voltage and Process
|
Yang, Wei-Bin |
| 淡江大學 |
2015-11-09 |
Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in UMC 0.18um CMOS Process
|
Yang, Wei-Bin;Lin, Yu-Yao;Wang, Chi-Hsiung;Chang, Kuo-Ning;Chen, Cing-Huan;Lo, Yu-Lung |
| 淡江大學 |
2015-10 |
A 25 MHz crystal less clock generator with background calibration against process and temperature variation
|
Yang, Wei-Bin; Hong, Ming-Hao |
顯示項目 1-25 / 79 (共4頁)
1 2 3 4 > >>
每頁顯示[10|25|50]項目
|
