| 淡江大學 |
2013-04-08 |
A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved
|
Yu-Lung Lo; Jhih-Wei Tsai; Han-Ying Liu; Yang, Wei-Bin |
| 淡江大學 |
2013-03 |
A new phase interpolator circuit for frequency multiplication design in embedded system
|
Yang, Wei-Bin; Wang, Chi-Hsiung; Xie, Shao-Jyun |
| 淡江大學 |
2013-01 |
Low-Power Fast-Settling Low-Dropout Regulator Using a Digitally Assisted Voltage Accelerator for DVFS Application
|
Yang, Wei-Bin; Wang, Chi Hsiung; Chang, Hsiang Hsiung; Hong, Ming Hao; Shen, Jsung Mo |
| 淡江大學 |
2012-11-04 |
A 300mV 10MHz 4kb 10T Subthreshold SRAM for Ultralow-Power Application
|
Yang, Wei-Bin |
| 淡江大學 |
2012-07-15 |
A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS
|
Yang, Wei-Bin |
| 淡江大學 |
2012 |
A Robust Oscillator for Embedded System without External Crystal
|
Yang, Wei-Bin; Wang, Chi-Hsiung; Chou, I-Ting |
| 淡江大學 |
2011-12-14 |
Temperature Insensitive Current Reference for the 6.27 MHz Oscillator
|
Yang, Wei-bin; Huang, Zheng-yi; Cheng, Ching-tsan; Lo, Yu-lung |
| 淡江大學 |
2011-12-13 |
Supply Voltage and Temperature Insensitive Current Reference for the 4 MHz Oscillator
|
Wang, Chi-hsiung; Lin, Cheng-feng; Yang, Wei-bin; Lo, Yu-lung |
| 淡江大學 |
2011-12 |
A New Temperature Independent Current Controlled Oscillator
|
Huang, Zheng-yi; Chiang, Jen-shiun; Yang, Wei-bin; Wang, Chi-hsiung |
| 淡江大學 |
2011-10 |
A synthesizable pseudo fractional-N clock generator with improved duty cycle output
|
Yang, Wei-Bin; Hsieh, Chang-Yo |
| 淡江大學 |
2011-06-20 |
The High-Performance and Low-Power CMOS Output Driver Design
|
Yang, Wei-bin; Liao, Pei-hsuan; Wang, Chi-hsiung; Cheng, Ching-tsan |
| 淡江大學 |
2011-01 |
A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process
|
Yang, Wei-Bin; Liao, Chao-Cheng; Liang, Yung-Chih |
| 淡江大學 |
2011 |
The High-Performance and Low-Power CMOS Output Driver Design
|
Cheng, Ching-tsan; Wang, Chi-hsiung; Liao, Pei-hsuan; Yang, Wei-bin; Lo, Yu-lung |
| 淡江大學 |
2010-11-21 |
A New Dynamic Fast-Settling Low Dropout Regulator with Programmable Output Voltage
|
Yang, Wei-bin; Shen, Jsung-mo; Chang, Hsiang-hsiung; Lo, Yu-lung |
| 淡江大學 |
2010-09 |
High Efficiency Concurrent Embedded Block Coding Architecture for JPEG 2000
|
Lin, Tsung-Da; Yang, Wei-Bin; Hsieh, Chang-Yu |
| 淡江大學 |
2010-03 |
A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output
|
Yang, Wei-Bin; Lo, Yu-Lung; Chao, Ting-Sheng |
| 淡江大學 |
2009-12 |
A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator
|
Shen, Jsung-mo; Yang, Wei-bin; Hsieh, Chang-yu; Lo, Yu-lung |
| 淡江大學 |
2009-12 |
A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
|
Gao, Wan-lun; Yang, Wei-bin; Lo, Yu-lung |
| 國立高雄師範大學 |
2009-12 |
A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
|
Wan-Lun Gao;Yang Wei-Bin;Yu-Lung Lo; 羅有龍 |
| 淡江大學 |
2009-09 |
Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique
|
Chao, Ting-sheng; Lo, Yu-lung; Yang, Wei-bin; Cheng, Kuo-hsing |
| 淡江大學 |
2009-08 |
A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator
|
Shen, Jsung-mo; Yang, Wei-bin; Hsieh, Chang-yu; Lo, Yu-lung |
| 淡江大學 |
2009-06 |
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
|
Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing |
| 淡江大學 |
2009-05 |
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique
|
Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing |
| 淡江大學 |
2008-11 |
A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage
|
Liang, Yung-chih; Huang, Ching-ji; Yang, Wei-bin |
| 淡江大學 |
2008-09-01 |
時脈產生器以及相關之鎖相迴路與時脈產生方法
|
郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing |
