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"yang wei bin"的相關文件
顯示項目 61-70 / 79 (共8頁)
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| 淡江大學 |
2008-07 |
A New Low Power, High Speed Double-Edge Triggered Flip-Flop
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Wu, Chung-Lin; Yang, Wei-Bin; Rau, Jiann-Chyi; Wang, Chi-Hsiung |
| 淡江大學 |
2008-04-16 |
A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
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Cheng, Kuo-hsing; Hung, Cheng-liang; Chang, Chih-hsien; Lo, Yu-lung; Yang, Wei-bin; Miaw, Jiunn-way |
| 淡江大學 |
2007-04 |
A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery
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Cheng, Kuo-Hsing; Chen, Chao-An; Yang, Wei-Bin; Cho, Feng-Hsin |
| 淡江大學 |
2006-12 |
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
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Jau, Ting-sheng; Yang, Wei-bin; Lo, Yu-lung |
| 淡江大學 |
2006-12 |
Analysis and Design of High Performance, Low Power Multiple Ports
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Jau, Ting-sheng; Yang, Wei-bin; Chang, Chung-yu |
| 淡江大學 |
2006-05 |
The new improved pseudo fractional-N clock generator with 50% duty cycle
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Kuo, Shu-chang; Hung, Tzu-chien; Yang, Wei-bin |
| 淡江大學 |
2005-09-23 |
Programmable fractional-N clock generators
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郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing |
| 淡江大學 |
2005-08-29 |
The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle
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Yang, Wei-bin; Kuo, Shu-chang; Chu, Yuan-hua; Cheng, Kuo-hsing |
| 淡江大學 |
2004-05 |
A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
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Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
| 淡江大學 |
2003-11 |
A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
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Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
顯示項目 61-70 / 79 (共8頁)
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