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Showing items 1-10 of 80 (8 Page(s) Totally)
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| 淡江大學 |
2024-12-02 |
A dual-loop CDR circuit with dual-mode capacitor multiplier-based loop filter and active inductor ring VCO
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Yang, Wei-Bin;Chuang, Che-Chia;Peng, Hsiao-Yen |
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2024-02 |
A High-Efficiency and Wide-Load Current Range LDO with Dynamic Loop Gain Control Technique
|
Yang, Wei-bin |
| 淡江大學 |
2023-10-21 |
A Multi-Stage Dual Mode Digital LDO with Fast Transient Response and Adaptive Frequency
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Yang, Wei-Bin;Chu, Li-Lun;Chen, Tse-Yu;Lin, Cheng-Kai;Roy, Diptendu Sinha |
| 淡江大學 |
2023-09-05 |
High-Efficiency and Wide-Load Current Range LDO Regulator with Dynamic Loop Gain Control Technique
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Chiu, Yu-Chun;Lo, Yu-Lung;Lin, Chia-Wen;Yang, Wei-Bin |
| 淡江大學 |
2022-09 |
A Programmable Multiple Frequencies Clock Generator with Process and Temperature Compensation Circuit for System on Chip Design
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Yang, Wei-Bin;Chang, Kuo-Ning;Yeh, Lu-Chun |
| 淡江大學 |
2021-12-03 |
Asynchronous Digital Low-Dropout Regulator with Dual Adjustment Mode in Ultra-Low Voltage Input
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Yang, Wei-Bin;Sun, Chi-Hsuan;Roy, Diptendu Sinha;Chen, Yi-Mei |
| 淡江大學 |
2020-03-06 |
A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications
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Yang, Wei-Bin;Wang, Hsi-Hua;Chang, Hsin-I;Lo, Yu-Lung |
| 淡江大學 |
2019-05-07 |
A Sensitivity-Power Efficiency Adjustable Wake-Up Receiver with Injection-Locked Oscillator Calibration
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Shih, Horng-Yuan;Chang, Yu-Chuan;Chen, Chieh-Chih;Yang, Wei-Bin |
Showing items 1-10 of 80 (8 Page(s) Totally)
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