| 淡江大學 |
2011-06-20 |
The High-Performance and Low-Power CMOS Output Driver Design
|
Yang, Wei-bin; Liao, Pei-hsuan; Wang, Chi-hsiung; Cheng, Ching-tsan |
| 淡江大學 |
2011-01 |
A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process
|
Yang, Wei-Bin; Liao, Chao-Cheng; Liang, Yung-Chih |
| 淡江大學 |
2011 |
The High-Performance and Low-Power CMOS Output Driver Design
|
Cheng, Ching-tsan; Wang, Chi-hsiung; Liao, Pei-hsuan; Yang, Wei-bin; Lo, Yu-lung |
| 淡江大學 |
2010-11-21 |
A New Dynamic Fast-Settling Low Dropout Regulator with Programmable Output Voltage
|
Yang, Wei-bin; Shen, Jsung-mo; Chang, Hsiang-hsiung; Lo, Yu-lung |
| 淡江大學 |
2010-09 |
High Efficiency Concurrent Embedded Block Coding Architecture for JPEG 2000
|
Lin, Tsung-Da; Yang, Wei-Bin; Hsieh, Chang-Yu |
| 淡江大學 |
2010-03 |
A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output
|
Yang, Wei-Bin; Lo, Yu-Lung; Chao, Ting-Sheng |
| 淡江大學 |
2009-12 |
A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator
|
Shen, Jsung-mo; Yang, Wei-bin; Hsieh, Chang-yu; Lo, Yu-lung |
| 淡江大學 |
2009-12 |
A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
|
Gao, Wan-lun; Yang, Wei-bin; Lo, Yu-lung |
| 國立高雄師範大學 |
2009-12 |
A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
|
Wan-Lun Gao;Yang Wei-Bin;Yu-Lung Lo; 羅有龍 |
| 淡江大學 |
2009-09 |
Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique
|
Chao, Ting-sheng; Lo, Yu-lung; Yang, Wei-bin; Cheng, Kuo-hsing |
| 淡江大學 |
2009-08 |
A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator
|
Shen, Jsung-mo; Yang, Wei-bin; Hsieh, Chang-yu; Lo, Yu-lung |
| 淡江大學 |
2009-06 |
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
|
Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing |
| 淡江大學 |
2009-05 |
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique
|
Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing |
| 淡江大學 |
2008-11 |
A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage
|
Liang, Yung-chih; Huang, Ching-ji; Yang, Wei-bin |
| 淡江大學 |
2008-09-01 |
時脈產生器以及相關之鎖相迴路與時脈產生方法
|
郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing |
| 淡江大學 |
2008-07 |
A New Low Power, High Speed Double-Edge Triggered Flip-Flop
|
Wu, Chung-Lin; Yang, Wei-Bin; Rau, Jiann-Chyi; Wang, Chi-Hsiung |
| 淡江大學 |
2008-04-16 |
A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
|
Cheng, Kuo-hsing; Hung, Cheng-liang; Chang, Chih-hsien; Lo, Yu-lung; Yang, Wei-bin; Miaw, Jiunn-way |
| 淡江大學 |
2007-04 |
A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery
|
Cheng, Kuo-Hsing; Chen, Chao-An; Yang, Wei-Bin; Cho, Feng-Hsin |
| 淡江大學 |
2006-12 |
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
|
Jau, Ting-sheng; Yang, Wei-bin; Lo, Yu-lung |
| 淡江大學 |
2006-12 |
Analysis and Design of High Performance, Low Power Multiple Ports
|
Jau, Ting-sheng; Yang, Wei-bin; Chang, Chung-yu |
| 淡江大學 |
2006-05 |
The new improved pseudo fractional-N clock generator with 50% duty cycle
|
Kuo, Shu-chang; Hung, Tzu-chien; Yang, Wei-bin |
| 淡江大學 |
2005-09-23 |
Programmable fractional-N clock generators
|
郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing |
| 淡江大學 |
2005-08-29 |
The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle
|
Yang, Wei-bin; Kuo, Shu-chang; Chu, Yuan-hua; Cheng, Kuo-hsing |
| 淡江大學 |
2004-05 |
A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
|
Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
| 淡江大學 |
2003-11 |
A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
|
Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
