臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立交通大學	2020-02-02T23:55:33Z	Fabrication of Omega-gated Negative Capacitance FinFETs and SRAM	Sung, P-J; Su, C-J; Lu, D. D.; Luo, S-X; Kao, K-H; Ciou, J-Y; Jao, C-Y; Hsu, H-S; Wang, C-J; Hong, T-C; Liao, T-H; Fang, C-C; Wang, Y-S; Huang, H-F; Li, J-H; Huang, Y-C; Hsueh, F-K; Wu, C-T; Ma, W. C-Y; Huang, K-P; Lee, Y-J; Chao, T-S; Li, J-Y; Wu, W-F; Yeh, W-K; Wang, Y-H
國立成功大學	2020	Process and Structure Considerations for the Post FinFET Era	Su, C.-J.;Sung, P.-J.;Kao, Kao K.-H.;Lee, Y.-J.;Wu, Wu W.-F.;Yeh, W.-K.
國立成功大學	2020	3D integration of vertical-stacking of MoS2and Si CMOS featuring embedded 2T1R configuration demonstrated on full wafers	Su, C.J.;Huang, M.K.;Lee, K.S.;Hu, V.P.H.;Huang, Y.F.;Zheng, B.C.;Yao, C.H.;Lin, N.C.;Kao, Kao K.H.;Hong, T.C.;Sung, P.J.;Wu, C.T.;Yu, T.Y.;Lin, K.L.;Tseng, Y.C.;Lin, C.L.;Lee, Y.J.;Chao, T.S.;Li, J.Y.;Wu, Wu W.F.;Shieh, J.M.;Wang, Y.H.;Yeh, W.K.
國立交通大學	2019-10-05T00:08:42Z	Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O-3 Treatment	Yeh, M. -S.; Luo, G. -L.; Hou, F. -J.; Sung, P. -J.; Wang, C. -J.; Su, C. -J.; Wu, C. -T.; Huang, Y. -C.; Hong, T. -C.; Chao, T. -S.; Chen, B. -Y.; Chen, K. -M.; Wu, Y. -C.; Izawa, M.; Miura, M.; Morimoto, M.; Ishimura, H.; Lee, Y. -J.; Wu, W. -F.; Yeh, W. -K.
國立交通大學	2019-06-03T01:09:17Z	A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node	Tang, Y. -T; Su, C. -J.; Wang, Y. -S.; Kao, K. -H.; Wu, T. -L.; Sung, P. -J.; Hou, F. -J.; Wang, C. -J.; Yeh, M. -S.; Lee, Y. -J.; Wu, W. -F.; Huang, G. -W.; Shieh, J. -M.; Yeh, W. -K.; Wang, Y. -H.
國立交通大學	2019-04-02T06:04:37Z	Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications	Sung, P. -J.; Chang, C. -Y.; Chen, L. -Y.; Kao, K. -H.; Su, C. -J.; Liao, T. -H.; Fang, C. -C.; Wang, C. -J.; Hong, T. -C.; Jao, C. -Y.; Hsu, H. -S.; Luo, S. -X.; Wang, Y. -S.; Huang, H. -F.; Li, J. -H.; Huang, Y. -C.; Hsueh, F. -K.; Wu, C. -T.; Huang, Y. -M.; Hou, F. -J.; Luo, G. -L.; Shen, Y. -L.; Ma, W. C. -Y.; Huang, K. -P.; Lin, K. -L.; Samukawa, S.; Li, Y.; Huang, G. -W; Lee, Y. -J.; Li, J. -Y.; Wu, W. -F.; Shieh, J. -M.; Chao, T. -S.; Yeh, W. -K.; Wang, Y. -H.
國立成功大學	2019	A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs	Tang, Y.-T.;Fan, C.-L.;Kao, Y.-C.;Modolo, N.;Su, C.-J.;Wu, T.-L.;Kao, Kao K.-H.;Wu, P.-J.;Hsaio, S.-W.;Useinov, A.;Su, P.;Wu, Wu W.-F.;Huang, G.-W.;Shieh, J.-M.;Yeh, W.-K.;Wang, Y.-H.
國立成功大學	2019	First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications	Chang, S.-W.;Li, J.-H.;Huang, M.-K.;Huang, Y.-C.;Huang, S.-T.;Wang, H.-C.;Huang, Y.-J.;Wang, J.-Y.;Yu, L.-W.;Huang, Y.-F.;Hsueh, F.-K.;Sung, P.-J.;Wu, C.-T.;Ma, W.C.-Y.;Kao, Kao K.-H.;Lee, Y.-J.;Lin, C.-L.;Chuang, R.W.;Huang, K.-P.;Samukawa, Samukawa S.;Li, Y.;Lee, W.-H.;Chu, T.-Y.;Chao, T.-S.;Huang, G.-W.;Wu, Wu W.-F.;Li, J.-Y.;Shieh, J.-M.;Yeh, W.-K.;Wang, Y.-H.;Lu, D.D.;Wang, C.-J.;Lin, N.-C.;Su, C.-J.;Lo, S.-H.;Huang, Huang H.-F.
國立成功大學	2019	Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications	Sung, P.-J.;Chang, Chang C.-Y.;Chen, L.-Y.;Kao, Kao K.-H.;Su, C.-J.;Liao, T.-H.;Fang, C.-C.;Wang, C.-J.;Hong, T.-C.;Jao, C.-Y.;Hsu, Hsu H.-S.;Luo, S.-X.;Wang, Y.-S.;Huang, Huang H.-F.;Li, J.-H.;Huang, Y.-C.;Hsueh, F.-K.;Wu, C.-T.;Huang, Y.-M.;Hou, F.-J.;Luo, G.-L.;Huang, Y.-C.;Shen, Y.-L.;Ma, W.C.-Y.;Huang, K.-P.;Lin, K.-L.;Samukawa, Samukawa S.;Li, Y.;Huang, G.-W.;Lee, Y.-J.;Li, J.-Y.;Wu, Wu W.-F.;Shieh, J.-M.;Chao, T.-S.;Yeh, W.-K.;Wang, Y.-H.
國立成功大學	2019	Fabrication of omega-gated negative capacitance finfets and SRAM	Sung, P.-J.;Su, C.-J.;Lu, D.D.;Luo, S.-X.;Kao, Kao K.-H.;Ciou, J.-Y.;Jao, C.-Y.;Hsu, Hsu H.-S.;Wang, C.-J.;Hong, T.-C.;Liao, T.-H.;Fang, C.-C.;Wang, Y.-S.;Huang, Huang H.-F.;Li, J.-H.;Huang, Y.-C.;Hsueh, F.-K.;Wu, C.-T.;Ma, W.C.-Y.;Huang, K.-P.;Lee, Y.-J.;Chao, T.-S.;Li, J.-Y.;Wu, Wu W.-F.;Yeh, W.-K.;Wang, Y.-H.
臺大學術典藏	2018-09-10T15:33:12Z	Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology	Hou, F.-J.; Chuang, S.-S.; Hsueh, F.-K.; Kao, K.-H.; Sung, P.-J.; Yuan, W.-Y.; Yao, J.-Y.; Lu, Y.-C.; Lin, K.-L.; Wu, C.-T.; Chen, H.-C.; Chen, B.-Y.; Huang, G.-W.; Chen, H.J.H.; Li, J.-Y.; Li, Y.; Samukawa, S.; Chao, T.-S.; Tseng, T.-Y.; Wu, W.-F.; Hou, T.-H.; Yeh, W.-K.; Lee, Y.-J.; JIUN-YUN LI et al.
國立交通大學	2018-08-21T05:56:59Z	Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability	Su, C. -J.; Hong, T. -C.; Tsou, Y. -C.; Hou, F. -J.; Sung, P. -J.; Yeh, M. -S.; Wan, C. -C.; Kao, K. -H.; Tang, Y. -T.; Chiu, C. -H.; Wang, C. -J.; Chung, S. -T.; You, T. -Y.; Huang, Y. -C.; Wu, C. -T.; Lin, K. -L.; Luo, G. -L.; Huang, K. -P.; Lee, Y. -J.; Chao, T. -S.; Wu, W. -F.; Huang, G. -W.; Shieh, J. -M.; Yeh, W. -K.; Wang, Y. -H.
國立交通大學	2018-08-21T05:56:39Z	High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications	Lee, Y. -J.; Hong, T. -C.; Hsueh, F. -K.; Sung, P. J.; Chen, C. -Y.; Chuang, S. -S.; Cho, T. -C.; Noda, S.; Tsou, Y. -C.; Kao, K. -H.; Wu, C. -T.; Yu, T. -Y.; Jian, Y. -L.; Su, C. -J.; Huang, Y. -M.; Huang, W. -H.; Chen, B. -Y.; Chen, M. -C.; Huang, K. -P.; Li, J. -Y.; Chen, M. -J.; Li, Y.; Samukawa, S.; Wu, W. -F.; Huang, G. -W.; Shieh, J. -M.; Tseng, T. -Y.; Chao, T. -S.; Wang, Y. -H.; Yeh, W. -K.
國立交通大學	2017-04-21T06:49:14Z	A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing	Lee, Y. -J.; Cho, T. -C.; Kao, K. -H.; Sung, P. -J.; Hsueh, F. -K.; Huang, P. -C.; Wu, C. -T.; Hsu, S. -H.; Huang, W. -H.; Chen, H. -C.; Li, Y.; Current, M. I.; Hengstebeck, B.; Marino, J.; Bueyueklimanli, T.; Shieh, J. -M.; Chao, T. -S.; Wu, W. -F.; Yeh, W. -K.
國立交通大學	2017-04-21T06:48:50Z	High Performance Silicon N-channel Gate-All-Around Junctionless Field Effect Transistors by Strain Technology	Sung, P. -J.; Cho, T. -C.; Chen, P. -C.; Hou, F. -J.; Lai, C. -H; Lee, Y. -J.; Li, Y.; Samukawa, S.; Chao, T. -S.; Wu, W. -F.; Yeh, W. -K.
國立成功大學	2017	High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications	Lee, Y.-J.;Hong, T.-C.;Hsueh, F.-K.;Sung, P.-J.;Chen, Chen C.-Y.;Chuang, S.-S.;Cho, T.-C.;Noda, S.;Tsou, Y.-C.;Kao, Kao K.-H.;Wu, C.-T.;Yu, T.-Y.;Jian, Y.-L.;Su, C.-J.;Huang, Y.-M.;Huang, W.-H.;Chen, B.-Y.;Chen, M.-C.;Huang, K.-P.;Li, J.-Y.;Chen, M.-J.;Li, Y.;Samukawa, Samukawa S.;Wu, Wu W.-F.;Huang, G.-W.;Shieh, J.-M.;Tseng, Tseng T.-Y.;Chao, T.-S.;Wang, Y.-H.;Yeh, W.-K.
國立成功大學	2017	Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION	Su, C.-J.;Tang, Y.-T.;Tsou, Y.-C.;Sung, P.-J.;Hou, F.-J.;Wang, C.-J.;Chung, S.-T.;Hsieh, C.-Y.;Yeh, Yeh Y.-S.;Hsueh, F.-K.;Kao, Kao K.-H.;Chuang, S.-S.;Wu, C.-T.;You, T.-Y.;Jian, Y.-L.;Chou, T.-H.;Shen, Y.-L.;Chen, B.-Y.;Luo, G.-L.;Hong, T.-C.;Huang, K.-P.;Chen, M.-C.;Lee, Y.-J.;Chao, T.-S.;Tseng, Tseng T.-Y.;Wu, Wu W.-F.;Huang, G.-W.;Shieh, J.-M.;Yeh, W.-K.;Wang, Y.-H.
國立成功大學	2017	Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon	Lin, C.-Y.;Zhu, X.;Tsai, S.-H.;Tsai, S.-P.;Lei, S.;Shi, Y.;Li, Li L.-J.;Huang, S.-J.;Wu, Wu W.-F.;Yeh, W.-K.;Su, Y.-K.;Wang, K.L.;Lan, Y.-W.
國立臺灣科技大學	2013	Reliability analysis of pHEMT power amplifier with an on-chip linearizer	Yuan, J.-S.;Wang, Y.;Steighner, J.;Yen, H.-D.;Jang, S.-L.;Huang, G.-W.;Yeh, W.-K.
國立高雄大學	2011-10	A Proposed High Manufacturability Strain Technology for High-k/Metal Gate SiGe-SOI CMOSFET	Yeh, W.K.; Cheng, C.Y.; Yang, Y.L.; Lin, C.T.; Lai, C.M.; Chen, Y.W.; Hsu, C.H.; Yang, C.W.; Chen, P.Y.
國立高雄大學	2009-11	Impact of Oxide Trap Charge on Performance of Strained Fully Depleted SOI Metal-Gate MOSFET	Yeh, W.K.; Wang, C.C.; Hsu, C.W.; Fang, Y.K.; Wu, S.M.; Ou, C.C.; Lin, C.L.; Gan, K.J.; Weng, C.J.; Chen, P.Y.; Yuan, J.S.; Liou, J.J.
國立高雄大學	2007	Efficient Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET	Yeh, W.K. ; Hsu, C.W. ; Lai, C.M. ; Lin, C.T. ; Fang, Y.K. ; Hsu, C.H. ; Chen, L.W. ; Huang, Y.T. ; Tsai, C.T.
國立高雄大學	2005	The impact of mobility modulation technology on device performance and reliability for sub-90nm SOI MOSFETs	Yeh, W.K. ; Lai, C.M. ; Lin, C.T. ; Fang, Y.K. ; Hu, H.H. ; Chen, K.M. ; Huang, G.W.

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