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Showing items 1-5 of 5 (1 Page(s) Totally) 1 View [10|25|50] records per page
國立臺灣大學 |
2003-12 |
A simulation-based temporal assertion checker for PSL
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Chang, Kai-Hui; Tu, Wei-Ting; Yeh, Yi-Jong; Kuo, Sy-Yen |
臺大學術典藏 |
2003-12 |
A simulation-based temporal assertion checker for PSL
|
Chang, Kai-Hui; Tu, Wei-Ting; Yeh, Yi-Jong; Kuo, Sy-Yen; Chang, Kai-Hui; Tu, Wei-Ting; Yeh, Yi-Jong; Kuo, Sy-Yen |
國立臺灣大學 |
2002 |
An Optimization-based Multiple-Voltage Scaling Technique for Low Power CMOS Digital Design
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Yeh, Yi-Jong; Kuo, Sy-Yen |
國立臺灣大學 |
2001-05 |
An optimization-based low-power voltage scaling technique using multiple supply voltages
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Yeh, Yi-Jong; Kuo, Sy-Yen |
臺大學術典藏 |
2001-05 |
An optimization-based low-power voltage scaling technique using multiple supply voltages
|
Yeh, Yi-Jong; Kuo, Sy-Yen; Yeh, Yi-Jong; Kuo, Sy-Yen |
Showing items 1-5 of 5 (1 Page(s) Totally) 1 View [10|25|50] records per page
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