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Showing items 1973746-1973755 of 2312825  (231283 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2018-09-10T07:08:34Z A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery Chih-Fan Liao;Shen-Iuan Liu; Chih-Fan Liao; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T07:08:34Z Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs SHEN-IUAN LIU; Liu, Shen-Iuan; Lin, Shao-Hung; Lin, Shao-Hung;Liu, Shen-Iuan
臺大學術典藏 2018-09-10T07:08:35Z A digitally calibrated 64.3-66.2GHz phase-locked loop Kun-Hung Tsai; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T07:08:35Z Frequency dividers with enhanced locking range Kun-Hung Tsai; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T07:08:36Z 93.5~ 109.4GHz CMOS injection-locked frequency divider with 15.3% locking range Lan-Chou Cho;Kun-Hung Tsai;Chao-Ching Hung;Shen-Iuan Liu; Lan-Chou Cho; Kun-Hung Tsai; Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T07:08:36Z A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers Jian-Hao Lu; Ke-Hou Chen; An-Ming Lee; Ting-Ying Wu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T07:08:36Z A dual-band 61.4~63GHz/ 75.5~77.5GHz CMOS receiver in a 90nm technology Ke-Hou Chen; Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T07:08:36Z A sub-1V low-dropout regulator with an on-chip voltage reference Wei-Jen Huang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T07:08:37Z 20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13μm CMOS Hong-Lin Chu;Chaung-Lin Hsieh;Shen-Iuan Liu; Hong-Lin Chu; Chaung-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏 2018-09-10T07:08:37Z A 57.1-59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique Chao-Ching Hung;Chihun Lee;Lan-Chou Cho;Shen-Iuan Liu; Chao-Ching Hung; Chihun Lee; Lan-Chou Cho; Shen-Iuan Liu; SHEN-IUAN LIU

Showing items 1973746-1973755 of 2312825  (231283 Page(s) Totally)
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