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顯示項目 1958676-1958685 / 2346410 (共234641頁)
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| 臺大學術典藏 |
2018-09-10T03:29:30Z |
The use of intermediate memories for low-latency memory access in supercomputer scalar units
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Sohi, G.S.;Hsu, W.-C.; Sohi, G.S.; Hsu, W.-C.; WEI-CHUNG HSU |
| 臺大學術典藏 |
2018-09-10T03:29:30Z |
Future general purpose supercomputer architectures
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Smith, J.E.;Hsu, W.-C.;Hsiung, C.; Smith, J.E.; Hsu, W.-C.; Hsiung, C.; WEI-CHUNG HSU |
| 臺大學術典藏 |
2018-09-10T03:29:30Z |
Demonstration and optimization of an optoelectronic phase-locked phase shifted for optical microwave signals
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Lin, G.-R.; Chang, Y.-C.; GONG-RU LIN |
| 臺大學術典藏 |
2018-09-10T03:29:31Z |
Exploitation of operation-level parallelism in a processor of the CRAY X-MP
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Vajapeyam, Sriram;Sohi, Gurindar S.;Hsu, Wei-Chung; Vajapeyam, Sriram; Sohi, Gurindar S.; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2018-09-10T03:29:31Z |
Hard ware-software timing co-verification of distributed embedded systems
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Jih-Ming, F.U.; Lee Trong-Yen; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:31Z |
Automatic router for the pin grid array package
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Chen, S.-S.; Chen, J.-J.; Tsai, C.-C.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:31Z |
Tutorial on VLSI partitioning
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Chen, S.-J.; Cheng, C.-K.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:32Z |
GM_Plan: A Gate Matrix Layout Algorithm Based on Artificial Intelligence Planning Techniques
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Hu, Y.H.;Chen, S.-J.; Hu, Y.H.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:32Z |
Generalized terminal connectivity problem for multilayer layout scheme
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Tsai, C.-C.;Chen, S.-J.;Feng, W.-S.; Tsai, C.-C.; Chen, S.-J.; Feng, W.-S.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:32Z |
Spontaneous bowel perforation in infants and young children: A clinicopathologic analysis of pathogenesis
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Chen, J.-C.;Chen, C.-C.;Liang, J.-T.;Huang, S.-F.; Jin-Tung Liang |
顯示項目 1958676-1958685 / 2346410 (共234641頁)
<< < 195863 195864 195865 195866 195867 195868 195869 195870 195871 195872 > >>
每頁顯示[10|25|50]項目
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