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显示项目 1973021-1973030 / 2346460 (共234646页)
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| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip routing with testability and yield enhancement
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Li, K.S.-M.; Lee, C.-L.; Chang, Y.-W.; Su, C.; Chen, J.-E.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip routing for the X-based architecture
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Ho, T.-Y.; Chang, C.-F.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip gridless routing considering optical proximity correction
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Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Modern floorplanning based on fast simulated annealing
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Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs
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Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
Delay modeling for buffered RLY/RLC trees
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Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
Crosstalk- and performance-driven multilevel full-chip routing
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Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.-T.; YAO-WEN CHANG; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
An exact jumper insertion algorithm for antenna effect avoidance/fixing
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Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
A routing algorithm for flip-chip design
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Fang, J.-W.; Lin, I.-J.; Yuh, P.-H.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
FPGA global routing based on a new congestion metric
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Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
显示项目 1973021-1973030 / 2346460 (共234646页)
<< < 197298 197299 197300 197301 197302 197303 197304 197305 197306 197307 > >>
每页显示[10|25|50]项目
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