| 國立高雄師範大學 |
2004 |
Chip-capacitor loaded dual-band microstrip antenna
|
Chih-Yu Huang;H. F. Tsai;M. H. Lin; 黃智裕 |
| 國立臺灣大學 |
2008-12 |
Chip-CE/MS using a flat low-sheath-flow interface
|
Li, F. A.; Huang, J. L.; Her, G. R. |
| 中華大學 |
2010 |
Chip-implementation of a self-tuning nonlinear function control for DC-DC converters
|
許駿飛; Hsu, Chun-Fei |
| 元智大學 |
2010-03 |
Chip-implementation of a self-tuning nonlinear function control for DC-DC converters
|
林志民; Chun-Fei Hsu; Shuen-Liang Wang; Ming-Chia Li |
| 國立中山大學 |
2009-04 |
Chip-inductor-embedded small-size printed strip monopole for WWAN operation in the mobile phone
|
T.W. Kang;K.L. Wong |
| 國立交通大學 |
2014-12-08T15:25:56Z |
Chip-interleaved WCDMA with parallel-interference-cancellation receiver in multipath Rayleigh fading channels
|
Lin, YN; Lin, DW |
| 國立暨南國際大學 |
2009 |
Chip-Level Channel Estimation for the Downlink of a WCDMA System in Very High Mobility Environment?
|
張進福; Chang, JF |
| 國立交通大學 |
2019-08-02T02:24:17Z |
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
|
Lin, T. W.; Ku, S. H.; Cheng, C. H.; Lee, C. W.; Ijen-Huang; Tsai, Wen-Jer; Lu, T. C.; Lu, W. P.; Chen, K. C.; Wang, Tahui; Lu, Chih-Yuan |
| 臺大學術典藏 |
2018-09-10T04:59:35Z |
Chip-level model of switching noise coupling on integrated system combining package and printed circuit board
|
S.-T. Chen; C.-W. Tsai; S.-M. Wu; C.-P. Hung; T.-L. Wu; TZONG-LIN WU |
| 國立交通大學 |
2014-12-12T03:05:59Z |
Chip-on-Glass（COG）彈性凸塊電性與可靠度之研究
|
林宗寬; Chung Kuang Lin; 陳智; Chih Chen |
| 臺大學術典藏 |
2018-09-10T07:02:57Z |
Chip-package-board co-design - A DDR3 system design example from circuit designers' perspective
|
Lin, Y.-H.; Chou, J.; Lu, Y.-C.; Wu, T.-L.; Chen, H.-S.; YI-CHANG LU; HSIN-SHU CHEN |
| 國立高雄師範大學 |
2005-06 |
Chip-package-board codesign of highly linear 3G-CDMA upconverter modules
|
Jian-Ming Wu;F. Y. Han;T. S. Horng;C. C. Tu;R. Chen;C.H. Chu; 吳建銘 |
| 國立中山大學 |
2005-06 |
Chip-package-board codesign of highly linear 3G-CDMA upconverter modules
|
F.Y. Han;J.M. Wu;T.S. Horng;C.C. Tu;R. Chen;C.H. Chu |
| 國立高雄師範大學 |
2005-10 |
Chip-Package-Board Codesign of W-CDMA RFICs
|
Jian-Ming Wu;F. Y. Han;T. S. Horng; 吳建銘 |
| 國立中山大學 |
2005-10 |
Chip-Package-Board Codesign of W-CDMA RFICs
|
F.Y. Han;J.M. Wu;T.S. Horng |
| 國立交通大學 |
2017-04-21T06:49:57Z |
Chip-Scale Nanophotonic Chemical and Biological Sensors using CMOS Process
|
Bollschweiler, Lincoln; English, Alex; Baker, R. Jacob; Kuang, Wan; Chang, Zi-Chang; Shih, Ming-Hsiung; Knowlton, William B.; Hughes, William L.; Lee, Jeunghoon; Yurke, Bernard; Cockerham, Nankyung Suh; Tyree, Vance C. |
| 國立交通大學 |
2019-04-03T06:47:17Z |
Chip-size wavelength detector based on a gradient grating period guided-mode resonance filter
|
Lin, Hsin-An; Hsu, Hsin-Yun; Huang, Cheng-Sheng |
| 國立交通大學 |
2019-04-02T06:04:30Z |
Chip-to-chip copper direct bonding in no-vacuum ambient using (111) oriented nano-twinned copper
|
Juang, Jing Ye; Shie, Kai Cheng; Li, Yu Jin; Lin, Benson; Chang, Chia Cheng; Tu, K. N.; Chen, Chih |
| 國立交通大學 |
2014-12-16T06:14:02Z |
Chip-to-chip multi-signaling communication system with common conductive layer
|
Su Chau-Chin; Ho Ying-Chieh; Huang Po-Hsiang |
| 國立交通大學 |
2014-12-16T06:15:14Z |
CHIP-TO-CHIP MULTI-SIGNALING COMMUNICATION SYSTEM WITH COMMON CONDUCTIVE LAYER
|
SU Chau-Chin; Ho Ying-Chieh; Huang Po-Hsiang |
| 南台科技大學 |
2004 |
Chip123 電子平台解決方案
|
李博明 |
| 國立臺灣大學 |
1986-09 |
Chipan Hydroelectric Project:Hydraulic Model Studies on Kuyuan Dam
|
王如意; Yen, Chin-Lien; Wang, Ru-Yih; Yen, Chin-Lien |
| 輔英科技大學 |
2008/8/1 |
chipball 誕生的過程
|
王照元 |
| 國立政治大學 |
2010 |
CHIPOTLE 墨西哥餐廳台北店商業計畫
|
陳浩仁; Chen, Hao-Jen |
| 國立交通大學 |
2014-12-08T15:36:18Z |
ChIPseek, a web-based analysis tool for ChIP data
|
Chen, Ting-Wen; Li, Hsin-Pai; Lee, Chi-Ching; Gan, Ruei-Chi; Huang, Po-Jung; Wu, Timothy H.; Lee, Cheng-Yang; Chang, Yi-Feng; Tang, Petrus |
