| 淡江大學 |
2009-06-26 |
Hardware accelerator design for image process
|
李世安 |
| 淡江大學 |
2012-08 |
Hardware accelerator design for image processing
|
Li, Shih-an; Wong, Ching-chang; Yang, Ching-yang; Chen, Li-feng |
| 淡江大學 |
2012-08 |
Hardware accelerator design for image processing
|
Li, Shih-An; Wong, Ching-Chang; Yang, Ching-Yang; Chen, Li-Feng |
| 淡江大學 |
2012-08 |
Hardware Accelerator Design for Image Processing
|
Li, S.A.; Wong, C.C.; Yang, C.Y.; Chen, L.F. |
| 淡江大學 |
2012-08-20 |
Hardware accelerator design for image processing
|
Li, S.A.;Wong, C.C.;Yang, C.Y.;Chen, L.F. |
| 國立高雄第一科技大學 |
2005.04 |
Hardware Accelerator for Vector Quantization by Using Pruned Look-Up Table
|
Wang, Pi-Chung;Lee, Chun-Liang;Chang, Hung-Yi;Chen, Tung-Shou; 張弘毅 |
| 國立高雄第一科技大學 |
2005-05 |
Hardware Accelerator for Vector Quantization by Using Pruned Look-Up Table
|
Wang, Pi-Chung;Lee, Chun-Liang;Chang, Hung-Yi;Chen, Tung-Shou; 張弘毅 |
| 南台科技大學 |
2017 |
Hardware and Software Cooperative Control System for Die-Cutting Machine Tool
|
Su, Chia-Hsiang; Lin, Horng-Horng; Liu, Yu-Shih |
| 國立臺灣大學 |
2008 |
Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies
|
Chang, Chen-Haur; Lee, Chuan-Yiu; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T07:03:44Z |
Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies
|
Chang, Chen-Haur; Lee, Chuan-Yiu; Chien, Shao-Yi; SHAO-YI CHIEN |
| 臺大學術典藏 |
2004-05 |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee; Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:21Z |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2003-05 |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Hsieh, Bing-Yu; Chen, Liang-Gee; Wang, Tu-Chih; Huang, Yu-Wen; Wang, Tu-Chih; Hsieh, Bing-Yu; Chen, Liang-Gee; Huang, Yu-Wen |
| 國立臺灣大學 |
2003-05 |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Huang, Yu-Wen; Wang, Tu-Chih; Hsieh, Bing-Yu; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Huang, Y.-W.; Wang, T.-C.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2004-08 |
Hardware architecture design for visual processing: present and future
|
Tseng, Po-Chih; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-08 |
Hardware architecture design for visual processing: present and future
|
Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:20Z |
Hardware architecture design for visual processing: Present and future
|
Tseng, P.-C.; Chen, L.-G.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2006-01 |
Hardware architecture design of an H.264/AVC video codec
|
Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee; Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee |
| 國立臺灣大學 |
2006-01 |
Hardware architecture design of an H.264/AVC video codec
|
Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T05:50:30Z |
Hardware architecture design of an H.264/AVC video codec
|
Chen, T.-C.; Lian Jr.; C.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2011 |
Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation
|
Hsu, Kung-Yen; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T08:42:33Z |
Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation
|
Hsu, Kung-Yen;Chien, Shao-Yi; Hsu, Kung-Yen; Chien, Shao-Yi; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T09:22:24Z |
Hardware architecture design of hybrid distributed video coding with frame level coding mode selection
|
Chiu, C.-C.; Wu, H.-F.; Chien, S.-Y.; Lee, C.-H.; Somayazulu, V.S.; Chen, Y.-K.; SHAO-YI CHIEN |
