| 臺大學術典藏 |
2018-09-10T05:17:59Z |
Low-Knudsen-number photophoresis of aerosol spheroids
|
Ou, C.L.; Keh, H.J.; HUAN-JANG KEH |
| 臺大學術典藏 |
2018-09-10T15:26:07Z |
Low-Latency Access and Flexible Resource Allocation with Fog-RAN
|
Hung-Yu Wei;Ai-Chun Pang; Hung-Yu Wei; Ai-Chun Pang; HUNG-YU WEI |
| 國立交通大學 |
2014-12-16T06:15:14Z |
LOW-LATENCY ARC-TANGENT CALCULATION STRUCTURE AND CALCULATION METHOD THEREOF
|
HSU TERNG-YIN; LAI WEI-CHI |
| 國立交通大學 |
2018-08-21T05:56:27Z |
Low-Latency Compressive Active User Identification over Frequency-Selective Fading Channels
|
Chang, Chun-Yi; Wu, Jwo-Yuh; Yang, Ming-Hsun; Wang, Tsang-Yi; Shao, Shuai; Maunder, Robert G. |
| 國立成功大學 |
2017 |
Low-latency implementation of 360 panoramic video viewing system
|
Tu, J.-S.;Lin, K.-S.;Lin, C.-L.;Kao, J.-Y.;Shih, G.-R.;Tsai, P.-H. |
| 國立中山大學 |
2007 |
Low-Latency Mobile IP Handover Based on Active-Scan Link Layer Assisted FMIPv6
|
Ming-Chun Hsia ; Chunhung Richard Lin |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules
|
Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2019-10-24T07:57:26Z |
Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine
|
吳安宇;AN-YEU(ANDY) WU;An-Yeu (Andy) Wu;Ding-Yuan Lee;Ting-Sheng Chen;Chia-Heng Wu; Chia-Heng Wu; Ting-Sheng Chen; Ding-Yuan Lee; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU; 吳安宇 |
| 臺大學術典藏 |
2020-06-11T06:34:18Z |
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine
|
Wu, C.-H.;Chen, T.-S.;Lee, D.-Y.;Liu, T.-T.;Wu, A.-Y.; Wu, C.-H.; Chen, T.-S.; Lee, D.-Y.; Liu, T.-T.; Wu, A.-Y.; TSUNG-TE LIU |
| 國立成功大學 |
2005-04-23 |
Low-latitude ELF-whistlers observed in Taiwan
|
Wang, Yun-Ching; Wang, Kaiti; Su, Han-Tzong; Hsu, Rue-Ron |
| 國立中山大學 |
2000 |
low-latitude ionospheric effects during a moderate storm by tomographic imaging
|
J.S. Xu;S.Y. Ma;X.B. Wu;K.H. Lin;K.C. Yeh |
| 國立成功大學 |
2014-06 |
Low-latitude midnight brightness in 630.0 nm limb observations by FORMOSAT-2/ISUAL
|
Rajesh, P. K.; Chen, C. H.; Lin, C. H.; Liu, J. Y.; Huba, J. D.; Chen, A. B.; Hsu, R. R.; Chen, Y. T. |
| 國立暨南國際大學 |
2003 |
Low-leakage 0.11 mu m CMOS for low-power RF-ICs and SRAMs applications?
|
林佑昇; Lin, YS |
| 國立彰化師範大學 |
2008-12 |
Low-Leakage and Low-Power Implementation of High-Speed 65nm Logic Gates
|
Wu, Tsung-Yi; Lu, Liang-Ying; Liang, Cheng-Hsun |
| 國立成功大學 |
2009-04 |
Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
|
Wu, Tsung-Yi; Lu, Liang-Ying |
| 國立彰化師範大學 |
2009 |
Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
|
Wu, Tsung-Yi ; Lu, Liang-Ying |
| 國立交通大學 |
2017-04-21T06:55:58Z |
Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process
|
Lin, Chun-Yu; Wu, Yi-Han; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:56:27Z |
Low-Leakage Bidirectional SCR With Symmetrical Trigger Circuit for ESD Protection in 40-nm CMOS Process
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立成功大學 |
2020 |
Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver With Less Delay of Clock Signals Used in AMLCDs
|
Deng;Ming-Yang;Liao;Wei-Sheng;Chen;Sung-Chun;Chang;Jui-Hung;Wu;Chia-En;Lin;Chih-Lung |
| 國立交通大學 |
2014-12-08T15:25:18Z |
Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou; Tang, Tien-Hao; Su, Kuan-Cheng |
| 義守大學 |
2009 |
Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology
|
Wang, Chang-Tzu ; Ker, Ming-Dou ; Tang, Tien-Hao ; Su, Kuan-Cheng |
| 國立交通大學 |
2014-12-08T15:25:16Z |
Low-leakage In(0.53)Ga(0.47)As p-i-n photodetector fabricated on GaAs substrate with linearly graded metamorphic In(x)Ga(1-x)P buffer
|
Lin, CK; Kuo, HC; Liao, YS; Lin, GR |
| 臺大學術典藏 |
2005 |
Low-leakage in0.53Ga0.47As p-i-n photodetector fabricated on GaAs substrate with linearly graded metamorphic in xGa1-xP buffer
|
Kuo, H.-C.; Liao, Y.-S.; Lin, G.-R.; GONG-RU LIN; Lin, C.-K. |
| 國立交通大學 |
2019-04-02T06:04:21Z |
Low-Leakage Power-Rail ESD Clamp Circuit With Gated Current Mirror in a 65-nm CMOS Technology
|
Aliolaguirre, Federico A.; Keri, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:55:42Z |
Low-Leakage Tetragonal ZrO2 (EOT < 1 nm) With In Situ Plasma Interfacial Passivation on Germanium
|
Chou, Chen-Han; Chang, Hao-Hsuan; Hsu, Chung-Chun; Yeh, Wen-Kuan; Chien, Chao-Hsin |
