| 臺大學術典藏 |
2022-05-19T07:46:28Z |
A 7.8-13.6 pJ/b Ultra-Low latency and reconfigurable neural network-assisted polar decoder with multi-code length support
|
Teng C.-F.; Wu A.-Y.; AN-YEU(ANDY) WU |
| 國立交通大學 |
2015-07-21T08:29:01Z |
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications
|
Lee, Xin-Ru; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi |
| 臺大學術典藏 |
2018-09-10T06:03:20Z |
A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.3-μm CMOS
|
T.-H. Lin; C.-C. Chi; TSUNG-HSIEN LIN |
| 國立臺灣大學 |
2005-02 |
A 70GHz cascaded multi-stage distributed amplifier in 90nm CMOS technology
|
Tsai, Ming-Da; Wang, Huei; Kuan, Jui-Feng; Chang, Chih-Sheng |
| 國立交通大學 |
2017-04-21T06:49:02Z |
A 70nW, 0.3V Temperature Compensation Voltage Reference Consisting of Subthreshold MOSFETs in 65nm CMOS Technology
|
Lu, Ting-Chou; Ker, Ming-Dou; Zan, Hsiao-Wen |
| 國立交通大學 |
2019-04-02T06:04:23Z |
A 70W and 90% GaN-Based Class-E Wireless-Power-Transfer System with Automatic-Matching-Point-Search Control for Zero-Voltage Switching and Zero-Voltage-Derivative Switching
|
Yeh, Che-Hao; Lin, Yen-Ting; Kuo, Chun-Chieh; Huang, Chao-Jen; Xie, Cheng-Yu; Lu, Shen-Fu; Yang, Wen-Hau; Chen, Ke-Horng; Liu, Kuo-Chi; Lin, Ying-Hsi |
| 國立交通大學 |
2018-08-21T05:56:23Z |
A 70W and 90% GaN-Based Class-E Wireless-Power-Transfer System with Automatic-Matching-Point-Search Control for Zero-Voltage Switching and Zero-Voltage-Derivative Switching
|
Yeh, Che-Hao; Lin, Yen-Ting; Kuo, Chun-Chieh; Huang, Chao-Jen; Xie, Cheng-Yu; Lu, Shen-Fu; Yang, Wen-Hau; Chen, Ke-Horng; Liu, Kuo-Chi; Lin, Ying-Hsi |
| 臺大學術典藏 |
2018-09-10T07:35:49Z |
A 71-76 GHz chip set for wireless communication in 65-nm CMOS technology
|
Kuo, J.-J.;Lin, W.-H.;Kuo, C.-C.;Tseng, J.R.;Tsai, Z.-M.;Lin, K.-Y.;Wang, H.; Kuo, J.-J.; Lin, W.-H.; Kuo, C.-C.; Tseng, J.R.; Tsai, Z.-M.; Lin, K.-Y.; Wang, H.; KUN-YOU LIN |
| 臺大學術典藏 |
2009 |
A 71-76 GHz chip set for wireless communication in 65-nm CMOS technology
|
Kuo, J.-J.; Lin, W.-H.; Kuo, C.-C.; Tseng, J.R.; Tsai, Z.-M.; Lin, K.-Y.; Wang, H.; HUEI WANG; Kuo, J.-J.;Lin, W.-H.;Kuo, C.-C.;Tseng, J.R.;Tsai, Z.-M.;Lin, K.-Y.;Wang, H. |
| 元智大學 |
2008-06 |
A 71-76 GHz CMOS variable gain amplifier using current steering technique
|
蔡政翰; Che-Chung Kuo; Zuo-Min Tsai; Huei Wang |
| 元智大學 |
2008-06 |
A 71-76 GHz CMOS variable gain amplifier using current steering technique
|
蔡政翰; Che-Chung Kuo; Zuo-Min Tsai; Huei Wang |
| 國立臺灣師範大學 |
2014-10-30T09:28:46Z |
A 71-76 GHz CMOS variable gain amplifier using current steering technique
|
Che-Chung Kuo; Zuo-Min Tsai; Jeng-Han Tsai; Huei Wang |
| 國立臺灣師範大學 |
2014-10-30T09:28:46Z |
A 71-76 GHz CMOS variable gain amplifier using current steering technique
|
Che-Chung Kuo; Zuo-Min Tsai; Jeng-Han Tsai; Huei Wang |
| 國立臺灣師範大學 |
2014-10-30T09:28:46Z |
A 71-76 GHz CMOS variable gain amplifier using current steering technique
|
Jeng-Han Tsai; Huei Wang; Zuo-Min Tsai; Che-Chung Kuo |
| 臺大學術典藏 |
2020-06-04T07:54:14Z |
A 71-76 GHz CMOS variable gain amplifier using current steering technique
|
Kuo, C.-C.;Tsai, Z.-M.;Tsai, J.-H.;Wang, H.; Kuo, C.-C.; Tsai, Z.-M.; Tsai, J.-H.; Wang, H.; HUEI WANG |
| 臺大學術典藏 |
2018-09-10T08:41:38Z |
A 71-80 GHz medium power amplifier using 4-mil 0.15-m GaAs-PHEMT technology
|
Wang, H.; KUN-YOU LIN; Tsai, Z.-M.;Lin, K.-Y.;Wang, H.; Tsai, Z.-M.; Lin, K.-Y. |
| 國立中山大學 |
2004-05 |
A 71nm Cross-Gate SOI MOSFET for 3D IC fabricated on a bulk wafer
|
Jyi-Tsong Lin;Jian-Han Huang |
| 國立臺灣大學 |
2007 |
A 71–80 GHz Amplifier Using 0.13- μm CMOS Technology
|
Wang, To-Po; Wang, Huei |
| 國立成功大學 |
2022-12 |
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier
|
Wang;Jia-Ching;Kuo;Tai-Haur |
| 國立交通大學 |
2014-12-08T15:47:31Z |
A 723-MHz 17.2-mW CMOS programmable counter
|
Chang, HH; Wu, JC |
| 國立交通大學 |
2019-04-02T05:59:24Z |
A 723-MHz 17.2-mW CMOS programmable counter
|
Chang, HH; Wu, JC |
| 臺大學術典藏 |
2022-08-05T08:59:03Z |
A 73-year-old man with bilateral posterior ankle pain
|
Chiu Y.-H.; TYNG-GUEY WANG |
| 國立交通大學 |
2020-05-05T00:02:26Z |
A 75-Gb/s/mm(2) and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm
|
Jou, Shyh-Jye Jerry; Chiu, Kang-Lun; Tsai, Pei-Yun; Lopez, Henry; Chan, Hsun-Wei |
| 國立臺灣大學 |
2008-06 |
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technique
|
Lee, Jri; Liu, M.; Wang, H. |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 75-GHz phase-locked loop in 90-nm CMOS technology
|
Lee, J.;Liu, M.;Wang, H.; Lee, J.; Liu, M.; Wang, H.; JRI LEE |
