|
顯示項目 714461-714470 / 2348973 (共234898頁)
<< < 71442 71443 71444 71445 71446 71447 71448 71449 71450 71451 > >>
每頁顯示[10|25|50]項目
| 臺大學術典藏 |
1986 |
Reconfigurable Cube-Connected Cycles Architectures
|
Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K.; 郭斯彥; Banerjee, P.;郭斯彥;Fuchs, W. K.; Banerjee, P.;Kuo, Sy-Yen;Fuchs, W. K.; Banerjee, P. |
| 國立臺灣大學 |
1991-01 |
Reconfigurable Cube-Connected Cycles Architectures
|
郭斯彥; Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K. |
| 國立臺灣大學 |
1986 |
Reconfigurable Cube-Connected Cycles Architectures
|
Banerjee, P.; 郭斯彥; Fuchs, W. K.; Banerjee, P.; Kuo, Sy-Yen; Fuchs, W. K. |
| 臺大學術典藏 |
2020-06-11T06:44:37Z |
Reconfigurable Cube-Connected Cycles Architectures.
|
Kuo, Sy-Yen;Fuchs, W. Kent; Kuo, Sy-Yen; Fuchs, W. Kent; SY-YEN KUO |
| 國立交通大學 |
2015-12-02T02:59:19Z |
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors
|
Wu, I-Wei; Shann, Jean Jyh-Jiun; Chung, Chung-Ping |
| 國立交通大學 |
2014-12-08T15:02:18Z |
Reconfigurable depth buffer compression design for 3D graphics system
|
Jung, Tzung-Rung; Van, Lan-Da; Fang, Wai-Chi; Shen, Teng-Yao |
| 臺大學術典藏 |
2004-05 |
Reconfigurable discrete cosine transform processor for object-based video signal processing
|
Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Reconfigurable discrete cosine transform processor for object-based video signal processing
|
Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:17Z |
Reconfigurable discrete cosine transform processor for object-based video signal processing
|
Tseng, P.-C.; Haung, C.-T.; Chen, L.-G.; LIANG-GEE CHEN; Tseng, P.-C.; Haung, C.-T.; Chen, L.-G. |
| 國立臺灣大學 |
2003-08 |
Reconfigurable discrete wavelet transform architecture for advanced multimedia systems
|
Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee |
顯示項目 714461-714470 / 2348973 (共234898頁)
<< < 71442 71443 71444 71445 71446 71447 71448 71449 71450 71451 > >>
每頁顯示[10|25|50]項目
|
