| 臺大學術典藏 |
2018-09-10T06:37:56Z |
Clock generator having a 50% duty-cycle
|
Tsung-Hsien Lin; TSUNG-HSIEN LIN |
| 中原大學 |
2002-08 |
Clock Period Minimization by Incorporating Clock Skew Scheduling and Gate-Level Delay Insertion
|
Huang, Shih-Hsu;Nieh, Yow-Tyng |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Clock Planning for Multi-Voltage and Multi-Mode Designs
|
Tsai, Chang-Cheng; Lin, Tzu-Hen; Tsai, Shin-Han; Chen, Hung-Ming |
| 國立中山大學 |
2004-12 |
Clock recovery and data recovery design for LVDS transceiver used in LCD panels
|
C.C. Wang;C.L. Lee;C.Y. Hsiao;J.F. Huang |
| 國立中山大學 |
2004-06 |
Clock recovery and data recovery design for LVDS transceiver used in LCD panels
|
C.C. Wang;C.L. Lee;C.Y. Hsiao;J.F. Huang |
| 臺大學術典藏 |
2018-09-10T09:25:33Z |
Clock Rescheduling for Timing Engineering Change Orders
|
Kuan-Hsien Ho;Xin-Wei Shih;Jie-Hong R. Jiang; Kuan-Hsien Ho; Xin-Wei Shih; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 元智大學 |
2010-03 |
Clock Routing for Structured ASICs with Via-Configurable Fabrics
|
林榮彬; I-Wei Lee; Wen-Hao Chen |
| 元智大學 |
2010-03 |
Clock Routing for Structured ASICs with Via-Configurable Fabrics
|
林榮彬; I-Wei Lee; Wen-Hao Chen |
| 國立臺灣科技大學 |
2012 |
Clock skew based client device identification in cloud environments
|
Huang, D.-J.;Yang, K.-T.;Ni, C.-C.;Teng, W.-C.;Hsiang, T.-R.;Lee, Y.-J. |
| 國立臺灣科技大學 |
2008-11-30 |
Clock Skew Based Node Identification in Wireless Sensor Networks
|
黃鼎傑;鄧惟中;王志元;黃炫諭;Joseph M. Hellerstein |
| 國立臺灣科技大學 |
2008 |
Clock Skew Based Node Identification in Wireless Sensor Networks
|
Ding-Jie Huang;Wei-Chung Teng;Chih-Yuan Wang;Hsuan-Yu Huang;Joseph M. Hellerstein |
| 國立臺灣科技大學 |
2008-11 |
Clock Skew Based Node Identification in Wireless Sensor Networks
|
Ding-Jie Huang;Wei-Chung Teng;Chih-Yuan Wang;Hsuan-Yu Huang;Hellerstein, J.M. |
| 國立臺灣科技大學 |
2008 |
Clock skew based node identification in wireless sensor networks
|
Huang D.-J.; Teng W.-C.; Wang C.-Y.; Huang H.-Y.; Hellerstein J.M. |
| 中原大學 |
2003-12 |
Clock Skew Scheduling for Peak Current Minimization
|
Chang, Chia-Ming;Huang, Shih-Hsu;Nieh, Yow-Tyng |
| 國立交通大學 |
2014-12-16T06:14:31Z |
Clock switching circuit
|
Wu; Jian-Hua; Hwang; Wei |
| 國立交通大學 |
2014-12-16T06:16:05Z |
Clock switching circuit
|
Wu, Jian-Hua; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:49:49Z |
Clock Synchronization by Phase Difference in Timing Estimation
|
Chang, Wen-Thong |
| 國立交通大學 |
2018-08-21T05:57:01Z |
Clock Tree Aware Post-Global Placement Optimization
|
Su, Hong-Yan; Chiang, Po-Ting; Samanta, Radhamanjari; Li, Yih-Lang |
| 國立交通大學 |
2015-07-21T11:21:03Z |
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
|
Wang, Chun-Kai; Chang, Yeh-Chi; Chen, Hung-Ming; Chin, Ching-Yu |
| 國立中山大學 |
2006 |
Clock-and-data recovery design for LVDS transceiver used in LCD panels
|
C.C. Wang;C.L. Lee;C.Y. Hsiao;J.F. Huang |
| 國立中山大學 |
2006-11 |
Clock-and-data recovery design for LVDS transceiver used in LCD panels
|
C.C. Wang;C.L. Lee;C.Y. Hsiao;J.F. Huang |
| 臺大學術典藏 |
2019-04-22T05:22:38Z |
Clock-aware placement for large-scale heterogeneous FPGAs
|
Chang, Y.-W.; Kuo, S.-Y.; Kuo, S.-Y.;Chiang, C.-H.;Chen, S.-C.;Huang, C.-C.;Kuo, Y.-C.;Chang, Y.-W.; Kuo, Y.-C.; Huang, C.-C.; Chen, S.-C.; Chiang, C.-H. |
| 臺大學術典藏 |
2021-09-02T00:09:07Z |
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs
|
Chen J;Lin Z;Kuo Y.-C;Huang C.-C;Chang Y.-W;Chen S.-C;Chiang C.-H;Kuo S.-Y.; Chen J; Lin Z; Kuo Y.-C; Huang C.-C; Chang Y.-W; Chen S.-C; Chiang C.-H; Kuo S.-Y.; YAO-WEN CHANG |
| 國立臺灣大學 |
2000 |
Clock-deskew buffer using a SAR-controlled delay-locked loop
|
Dehng, Guang-Kaai; Hsu, June-Ming; Yang, Ching-Yuan; Liu, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T08:42:12Z |
Clock-free RZ-BPSK data generation using self-starting optoelectronic oscillator
|
GONG-RU LIN; Lin, G.-R.; Chi, Y.-C.;Peng, P.-C.;Lin, G.-R.; Chi, Y.-C.; Peng, P.-C. |
