| 國立交通大學 |
2014-12-08T15:26:34Z |
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
|
Ker, MD; Chuang, CH; Hsu, KC; Lo, WY |
| 國立交通大學 |
2014-12-08T15:25:20Z |
ESD protection design for mixed-voltage I/O interfaces - Overview
|
Ker, Ming-Dou; Lin, Kun-Hsien |
| 國立交通大學 |
2014-12-08T15:26:14Z |
ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique
|
Ker, MD; Hsu, HC |
| 國立交通大學 |
2015-07-21T08:31:29Z |
ESD Protection Design for Radio-Frequency Integrated Circuits in Nanoscale CMOS Technology
|
Lin, Chun-Yu; Chu, Li-Wei; Tsai, Shiang-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Wei, Yu-Lin; Chang, Tzu-Heng |
| 國立交通大學 |
2017-04-21T06:56:36Z |
ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test
|
Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi |
| 國立交通大學 |
2017-04-21T06:48:45Z |
ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process
|
Chu, Li-Wei; Lin, Chun-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Tseng, Jen-Chou; Jou, Chewn-Pu; Tsai, Ming-Hsien |
| 國立交通大學 |
2019-10-05T00:09:47Z |
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications
|
Hung, Tao-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:18:35Z |
ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS
|
Ker, MD; Chang, WJ |
| 國立交通大學 |
2014-12-08T15:44:57Z |
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
|
Ker, MD; Chen, TY; Wu, CY; Chang, HH |
| 國立交通大學 |
2018-08-21T05:57:09Z |
ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process
|
Hung, Tao-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:38:36Z |
ESD protection design to overcome internal damage on interface circuits,of a CMOS IC with multiple separated power pins
|
Ker, MD; Chang, CY; Chang, YS |
| 國立交通大學 |
2014-12-08T15:26:36Z |
ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins
|
Ker, MD; Chang, CY; Chang, YS |
| 國立交通大學 |
2019-08-02T02:18:28Z |
ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains
|
Chen, Jie-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:12Z |
ESD Protection Design with Latchup-Free Immunity in 120V SOI Process
|
Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2014-12-08T15:38:25Z |
ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 義守大學 |
2010-12 |
ESD Protection Design with Lateral DMOS Transistor in 40-V BCD Technology
|
Chang-Tzu Wang;Ming-Dou Ker |
| 國立交通大學 |
2019-04-02T06:04:53Z |
ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications
|
Ker, Ming-Don; Lin, Chun-Yu; Wu, Yi-Han; Wang, Wen-Tai |
| 國立交通大學 |
2014-12-08T15:11:24Z |
ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
|
Ker, Ming-Dou; Chang, Wei-Jen |
| 國立交通大學 |
2017-04-21T06:55:35Z |
ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:10Z |
ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:26:55Z |
ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design
|
Chen, TY; Ker, MD |
| 國立交通大學 |
2014-12-16T06:15:12Z |
ESD PROTECTION STRUCTURE FOR 3D IC
|
Chen Kuan-Neng; Lai Ming-Fang; Chen Hung-Ming |
| 國立交通大學 |
2014-12-08T15:25:32Z |
ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications
|
Ker, MD; Chang, WJ; Yang, M; Chen, CC; Chan, MC; Shieh, WT; Yen, KL |
| 國立交通大學 |
2014-12-08T15:28:05Z |
ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process
|
Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Chang, Tzu-Heng |
| 國立交通大學 |
2014-12-08T15:43:41Z |
ESD protection under grounded-up bond pads in 0.13 mu m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology
|
Chou, KY; Chen, MJ |
| 大葉大學 |
2000 |
ESD robustness designs of power MOSFET ICs
|
陳勝利 |
| 大葉大學 |
2000-11 |
ESD Robustness Designs of Power MOSFET ICs
|
陳勝利 |
| 國立成功大學 |
2024 |
ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology
|
Chen;S, -H.;Fu;P, -Y.;Tsiara;A;Peer, van de;M;Simicic;M;Musibau;S;Ban;Y;Kao;K, -H.;Chen;W, -C.;Serbulova;K;Campenhout, Van;J;Absil;P;Croes;K |
| 國立交通大學 |
2014-12-08T15:15:20Z |
ESD robustness of thin-film devices with different layout structures in LTPS technology
|
Deng, Chih-Kang; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:48:20Z |
ESD Self-Protection Design on 2.4-GHz T/R Switch for RF Application in CMOS Process
|
Lin, Chun-Yu; Liu, Rui-Hong; Ker, Ming-Dou |
| 亞洲大學 |
2010-10 |
ESD Simulation on GGNMOS for 40V BCD
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 國立交通大學 |
2014-12-08T15:26:50Z |
ESD test methods on integrated circuits: An overview
|
Ker, MD; Peng, JH; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:23:05Z |
ESD-Aware Circuit Design in CMOS Integrated Circuits to Meet System-Level ESD Specification in Microelectronic Systems
|
Ker, Ming-Dou |
| 國立交通大學 |
2018-08-21T05:57:09Z |
ESD-Induced Latchup-Like Failure in a Touch Panel Control IC
|
Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi |
| 國立交通大學 |
2014-12-08T15:15:20Z |
ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
|
Ker, Ming-Dou; Hsiao, Yuan-Wen; Wu, Woei-Lin |
| 大葉大學 |
2007-01-26 |
ESD/TLP量測儀器及電子元件抗ESD分析研究
|
王光一, 陳勝利 許崇宜 |
| 中國文化大學 |
2006-06-30 |
ESD靜電防護材料之製備及其抗靜電性質之研究
|
邢文灝; 莊佾宸 |
| 臺大學術典藏 |
1989-09 |
ESEMAP:An Expert System for Emergency Management of Air Pollution
|
Wang, J. C.; Huang, Han-Pang; Li, Chang-Sheng; 黃漢邦; Wang, J. C.; 李常聲; Huang, Han-Pang; Li, Chang-Sheng |
| 國立臺灣大學 |
1990 |
ESEMAP:An Expert System for Emergency Management of Air Pollution
|
梁文傑; 黃孝平; Wang, J. C.; Liang, Wen-Jey; Huang, Hsiao-Ping; Wang, J. C. |
| 國立臺灣大學 |
1989-09 |
ESEMAP:An Expert System for Emergency Management of Air Pollution
|
黃漢邦; Wang, J. C.; 李常聲; Huang, Han-Pang; Wang, J. C.; Li, Chang-Sheng |
| 國立交通大學 |
2018-08-21T05:52:55Z |
eSES: Enhanced Simple Energy Saving for LTE HeNBs
|
Lin, Yi-Bing; Wang, Li-Chang; Chen, Wei-Cheng |
| 國立臺灣科技大學 |
2014 |
ESFM: An Essential Software Framework for Meshfree Methods
|
Hsieh, Y.-M.;Pan, M.-S. |
| 淡江大學 |
2025-08-29 |
ESG Disclosure Frequency and Its Association with Market Performance: Evidence from Taiwan
|
Liao, Chih-Feng |
| 淡江大學 |
2023-04-18 |
ESG Effects on Stock Prices During the Epidemic: Empirical Investigations for the Finance Holding Companies in Taiwan
|
Lin, Yen-ling |
| 致理技術學院 |
2022-09 |
ESG ETF之績效對比與其所包含之公司永續計畫
|
陳霈容, 張瑀珊,陳琪雯,游盛堯,郭子睿 |
| 淡江大學 |
2024-03-30 |
ESG Measurement, Peer Effects, and Strategic Financial Management: Lessons from Taiwan
|
Chang, Yu-Shan;Forgione, Dana A. |
| 淡江大學 |
2024-08-12 |
ESG Measurement, Peer Effects, and Strategic Financial Management: Lessons from Taiwan
|
Chang, Yu-Shan;Forgione, Dana |
| 中國科技大學 |
2023-07-31 |
ESG 、 法人持股與 公司價值 關聯性之實證研究
|
王昱隆 |
| 中國文化大學 |
2023 |
ESG 原則是否對股東財富有影響? 以台灣上市櫃公司為主
|
鄭棋陽 |
| 國立成功大學 |
2022-06-21 |
ESG 報導與企業法遵行為
|
詹彥莛; Ching, Yan-Ting Angie |
