| 義守大學 |
2010-05 |
Hardware Implementation of RFID Mutual Authentication Protocol
|
Yu-Jung Huang;Ching-Chien Yuan;Ming-Kun Chen;Wei-Cheng Lin;Hsien-Chiao Teng |
| 臺大學術典藏 |
2003-09 |
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-09 |
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 義守大學 |
2010-11 |
Hardware implementation of triangulation method based on CORDIC algorithm
|
Yen-Chang Huang;Chien-Chang Lai;Yu-Jung Huang |
| 中華大學 |
2004 |
Hardware Implementation of Viterbi Decoder for WLAN 802.11a
|
陳棟洲; Chen, Tung-Chou |
| 臺大學術典藏 |
2005-12 |
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
|
Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee; Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee |
| 國立臺灣大學 |
2005-12 |
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
|
Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
|
Chen, Y.-H.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2003-07 |
Hardware oriented rate control algorithm and implementation for realtime video coding
|
Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee; Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-07 |
Hardware oriented rate control algorithm and implementation for realtime video coding
|
Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware oriented rate control algorithm and implementation for realtime video coding
|
Fang, H.-C.; Wang, T.-C.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立中山大學 |
1999-11 |
Hardware realization of a bit-serial 16-bit multiplier using low-power high-speed FPGA logic module for DSP applications
|
C.C. Wang;C.J. Huang;H.L. Wu;H.M. Yang |
| 國立中山大學 |
1996-05 |
Hardware realization of multi-valued exponential bidirectional associative memory using current-mode circuits
|
C.C. Wang;Y.C. Chen |
| 國立臺灣科技大學 |
2012 |
Hardware resource manager for reconfiguration system
|
Lin, C.-T.;Horng, S.-J.;Huang, Y.-L. |
| 國立交通大學 |
2014-12-08T15:27:49Z |
HARDWARE SHARING IN TREE-STRUCTURE QMF BANKS
|
LEE, HR; JEN, CW |
| 國立臺灣科技大學 |
2009-04 |
Hardware Simplification to the Delta Path in a MASH 111 Delta–Sigma Modulator
|
Chia-Yu Yao;Chih-Chun Hsieh |
| 國立臺灣大學 |
2009 |
HARDWARE SOFTWARE CO-DESIGN OF A MULTIMEDIA SOC PLATFORM
|
Chen, Sao-Jie; Lin, Guang-Huei; Hsiung, Pao-Ann; Hu, Yu–Hen |
| 臺大學術典藏 |
2018-09-10T07:36:33Z |
Hardware software co-design of a multimedia SOC platform
|
Hu, Yu-Hen;Hsiung, Pao-Ann;Lin, Guang-Huei;Chen, Sao-Jie; Hu, Yu-Hen; Hsiung, Pao-Ann; Lin, Guang-Huei; Chen, Sao-Jie; Chen, Sao-Jie |
| 臺大學術典藏 |
1993-10 |
Hardware verification using symbolic state transition graphs
|
Chen, Pin-Hong; Shyu, Jyuo-Min; Chen, Liang-Gee; Chen, Pin-hong; Shyu, Jyuo-Min; Chen, Liang-Gee |
| 國立臺灣大學 |
1993-10 |
Hardware verification using symbolic state transition graphs
|
Chen, Pin-hong; Shyu, Jyuo-Min; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:49Z |
Hardware verification using symbolic state transition graphs
|
Chen, Pinhong; Shyu, Jyuo-Min; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2020-06-11T06:29:41Z |
Hardware Verification Using Symbolic State Transition Graphs.
|
Chen, Pinhong;Shyu, Jyuo-Min;Chen, Liang-Gee; Chen, Pinhong; Shyu, Jyuo-Min; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2021-09-21T23:19:35Z |
Hardware- And Memory-Efficient Architecture for Disparity Estimation of Large Label Counts
|
Wu, Sih Sian; Chen, Hon Hui; LIANG-GEE CHEN |
| 臺大學術典藏 |
2020-05-04T08:04:29Z |
Hardware-accelerated cache simulation for multicore by FPGA
|
Hung, S.-H.; Ho, Y.-M.; Yeh, C.-W.; Cheng-Yueh, Lee, C.-P.; SHIH-HAO HUNG |
