| 國立交通大學 |
2014-12-08T15:27:47Z |
A 1.5 V CMOS balanced differential switched-capacitor filter with internal clock boosters
|
WU, CY; WEY, WS; YU, TC |
| 國立交通大學 |
2014-12-08T15:27:46Z |
A 1.5 v CMOS current-mode cyclic analog-to-digital converter with digital error correction
|
CHEN, CC; WU, CY; CHO, JJ |
| 國立臺灣大學 |
1997-08 |
A 1.5 V CMOS high-speed 16-bit÷8-bit divider using the quotient-select architecture and true-single-phase bootstrapped dynamic circuit techniques suitable for low-voltage VLSI
|
Yeh, C.C.; Lou, J.H.; Kuo, J.B. |
| 國立臺灣大學 |
2008-12 |
A 1.5-9.6 GHz monolithic active quasi-circulator in 0.18 μm CMOS technology
|
Shin, Shih-Chieh; Huang, Jhih-Yu; Lin, Kun-You; Wang, Huei |
| 臺大學術典藏 |
2018-09-10T08:19:02Z |
A 1.5-mW, 23.6% Frequency Locking Range, 24-GHz Injection-Locked Frequency Divider
|
Yen-Hung Kuo;Jeng-Han Tsai;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; TIAN-WEI HUANG |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
A 1.5-mW, 23.6% frequency locking range,24-GHz injection-locked frequency divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
A 1.5-mW, 23.6% frequency locking range,24-GHz injection-locked frequency divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 臺大學術典藏 |
2006-05 |
A 1.5-V 10-ppm//spl deg/C 2nd-order curvature-compensated CMOS bandgap reference with trimming
|
Hsiao, Sen-Wen; Huang, Yen-Chih; Liang, David; Chen, H.W.K.; Chen, Hsin-Shu; Hsiao, Sen-Wen; Huang, Yen-Chih; Liang, David; Chen, H.W.K.; Chen, Hsin-Shu |
| 國立臺灣大學 |
2006-05 |
A 1.5-V 10-ppm//spl deg/C 2nd-order curvature-compensated CMOS bandgap reference with trimming
|
Hsiao, Sen-Wen; Huang, Yen-Chih; Liang, David; Chen, H.W.K.; Chen, Hsin-Shu |
| 國立交通大學 |
2014-12-08T15:48:10Z |
A 1.5-V 3 similar to 10-GHz 0.18-mu m CMOS Frequency Synthesizer for MB-OFDM UWB Applications
|
Huang, Zue-Der; Kuo, Fong-Wei; Wang, Wen-Chieh; Wu, Chung-Yu |
| 臺大學術典藏 |
1999-05 |
A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation
|
J. H. Lou; J. B. Kuo; JAMES-B KUO |
| 國立臺灣大學 |
1999 |
A 1.5-V CMOS all-N-logic true-single-phase bootstrappeddynamic-logic circuit suitable for low supply voltage and high-speedpipelined system operation
|
Lou, J.H.; Kuo, J.B. |
| 國立交通大學 |
2014-12-08T15:47:31Z |
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
|
Tseng, YK; Wu, CY |
| 國立交通大學 |
2019-04-02T05:59:23Z |
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
|
Tseng, YK; Wu, CY |
| 國立臺灣科技大學 |
2009 |
A 1.5-V transformer-based ultra-wideband LNA chip design
|
Huang J.-F.; Shie P.-J.; Liu R.-Y. |
| 國立交通大學 |
2014-12-08T15:27:05Z |
A 1.5-V, 2.4GHz CMOS low-noise amplifier
|
Yang, JN; Lee, CY; Hsu, TY; Hsu, TR; Wang, CC |
| 臺大學術典藏 |
2021-09-02T00:04:03Z |
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots
|
Chung C;Yang C.-H.; Chung C; Yang C.-H.; CHIA-HSIANG YANG |
| 國立臺灣大學 |
2009 |
A 1.5GHz all-digital spread spectrum clock generator
|
Lin, Sheng-You; Liu, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T07:41:58Z |
A 1.5GHz all-digital spread spectrum clock generator
|
Sheng-You Lin;Shen-Iuan Liu; Sheng-You Lin; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T07:41:58Z |
A 1.5GHz phase-locked loop with leakage current suppression in 65nm CMOS
|
Jung-Yu Chang;Shen-Iuan Liu; Jung-Yu Chang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立交通大學 |
2014-12-08T15:20:50Z |
A 1.5V 7.5uW Programmable Gain Amplifier for Multiple Biomedical Signal Acquisition
|
Kao, Shuo-Ting; Lu, Hungwen; Su, ChauChin |
| 國立交通大學 |
2014-12-08T15:27:27Z |
A 1.5V differential cross-coupled bootstrapped BiCMOS logic
|
Tseng, YK; Wu, CY |
| 臺大學術典藏 |
2021-02-26T08:42:04Z |
A 1.5£gJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots
|
Chung, C.; Yang, C.-H.; CHIA-HSIANG YANG |
| 國立臺灣大學 |
2008 |
A 1.5–9.6 GHz Monolithic Active Quasi-Circulator in 0.18μm CMOS Technology
|
Shin, Shih-Chieh; Huang, Jhih-Yu; Lin, Kun-You; Wang, Huei |
| 國立成功大學 |
2021 |
A 1.6-Gs/s 8b flash-SAR time-interleaved ADC with top-plate residue based gain calibration
|
Hsu, C.-W.;Chang, S.-J. |
