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"羅有龍"

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Institution	Date	Title	Author
國立高雄師範大學	2012-06-01	A 50ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit	Yu-Lung Lo;Pin-Tseng Chen;Chia-Chen Chan;Han-Ying Liu; 羅有龍
國立高雄師範大學	2012-06	A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique	Pin-Tseng Chen;Chia-Chen Chang;Han-Ying Liu;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2011-12	An All-Digital DLL with Dual-Loop Control for Multiphase Clock Generator	Yu-Lung Lo;Pei-Yuan Chou;Hsiang-Hui Cheng;Shu-Fen Tsai;Wei-Bin Yang; 羅有龍
國立高雄師範大學	2011-12	Supply Voltage and Temperature Insensitive Current Reference for the 4 MHz Oscillator	Chi-Hsiung Wang;Cheng-Feng Lin;Wei-Bin Yang;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2011-12	Temperature Insensitive Current Reference for the 6.27 MHz Oscillator	Ching-Tsan Cheng;Zheng-Yi Huang;Wei-Bin Yang;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2011-08	以延遲鎖定迴路為基礎之低功率小面積全數位可程式化時脈產生器研製	羅有龍; Yu-Lung Lo
國立高雄師範大學	2011-06	The High-Performance and Low-Power CMOS Output Driver Design	Ching-Tsan Chen;Chi-Hsiung Wang;Pei-Hsuan Liao;Wei-Bin Yang;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2011-03	A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip	Kuo-Hsing Chen;Yu-Chang Tsai;Yu-Lung Lo;Jing-Shiuan Huang; 羅有龍
國立高雄師範大學	2010-12	Dynamic Frequency Tracking and Phase Error Compensation Clock De-skew Buffer	Kuo-Hsing Cheng;Kai-Wei Hong;Yu-Lung Lo;Chen-Lung Wu;Chien-Hsien Lee; 羅有龍
國立高雄師範大學	2010-11	A New Dynamic Fast-Settling Low Dropout Regulator with Programmable Output Voltage	Hsiang-Hsiung Chang;Jsung-Mo Shen;Wei-Bin Yang;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2010-10	具多重相位輸出之寬頻全數位延遲鎖定迴路研製	羅有龍; Yu-Lung Lo
國立高雄師範大學	2010-03	A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output	Wei-Bin Yang;Yu-Lung Lo;Ting-Sheng Chao; 羅有龍
國立高雄師範大學	2009-12	A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller	Wan-Lun Gao;Yang Wei-Bin;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2009-12	A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator	Jsung-Mo Shen;Wei-Bin Yang;Chang-Yu Hsieh;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2009-09	Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique	Ting-Sheng Chao;Yu-Lung Lo;Wei-Bin Yang;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2009-08	A 0.5 V Phase-Locked Loop in 90nm CMOS Process	Kuo-Hsing Cheng;Jing-Shiuan Huang;Yu-Chang Tsai;Chao-Chang Chiu;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2009-08	A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator	Jsung-Mo Shen;Wei-Bin Yang;Chang-Yu Hsieh;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2009-06	High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2009-05	Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2009-02	Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System	Shu-Yu Jiang;Chan-Wei Huang;Yu-Lung Lo;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2008-08	Ultra-Low-Voltage Phase-Locked Loop with Bulk-Input VCO	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Jiunn-Way Miaw;Jing-Shiuan Huang;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2008-04	Spread-Spectrum Clock Generator Using Fractional–N PLL Controlled Delta-Sigma Modulator for Serial-ATA III	Kuo-Hsing Cheng;Cheng-Laing Hung;Chih-Hsien Chang;Yu-Lung Lo;Wei-Bin Yang;Jiunn-Way Miaw; 羅有龍
國立高雄師範大學	2007-12	A Phase Interpolator for Sub-1V and High Frequency for Clock and Data Recovery	Kuo-Hsing Cheng;Pei-Kai Tseng;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2007-11	Analysis and Design of Ultra Low VDD Circuit	Ting-Sheng Chao;Chung-Yu Chang;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2007-07	A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency Range Selector for Multiphase Clock Generator	Kuo-Hsing Chen;Yu-Lung Lo; 羅有龍

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