臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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"羅有龍"

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Showing items 26-35 of 49 (5 Page(s) Totally)
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Institution	Date	Title	Author
國立高雄師範大學	2009-08	A 0.5 V Phase-Locked Loop in 90nm CMOS Process	Kuo-Hsing Cheng;Jing-Shiuan Huang;Yu-Chang Tsai;Chao-Chang Chiu;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2009-08	A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator	Jsung-Mo Shen;Wei-Bin Yang;Chang-Yu Hsieh;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2009-06	High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2009-05	Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2009-02	Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System	Shu-Yu Jiang;Chan-Wei Huang;Yu-Lung Lo;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2008-08	Ultra-Low-Voltage Phase-Locked Loop with Bulk-Input VCO	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Jiunn-Way Miaw;Jing-Shiuan Huang;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2008-04	Spread-Spectrum Clock Generator Using Fractional–N PLL Controlled Delta-Sigma Modulator for Serial-ATA III	Kuo-Hsing Cheng;Cheng-Laing Hung;Chih-Hsien Chang;Yu-Lung Lo;Wei-Bin Yang;Jiunn-Way Miaw; 羅有龍
國立高雄師範大學	2007-12	A Phase Interpolator for Sub-1V and High Frequency for Clock and Data Recovery	Kuo-Hsing Cheng;Pei-Kai Tseng;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2007-11	Analysis and Design of Ultra Low VDD Circuit	Ting-Sheng Chao;Chung-Yu Chang;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2007-07	A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency Range Selector for Multiphase Clock Generator	Kuo-Hsing Chen;Yu-Lung Lo; 羅有龍

Showing items 26-35 of 49 (5 Page(s) Totally)
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