| 亞洲大學 |
201302 |
Accurate equivalent circuit model of deep trench capacitor by numerical simulation and analytical calculation
|
Fathna, Ashif;Fathna, Ashif;kumar, Vikash;kumar, Vikash;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
201302 |
Novel structure of deep trench capacitor with higher breakdown and higher capacitance density for Low Dropout Voltage regulator
|
Fathna, Ashif;Fathna, Ashif;kumar, Vikash;kumar, Vikash;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-10 |
A Novel Ultra High Voltage Sidewall Implant Super Junction MOSFET Using Arsenic Implantation under Trench Bottom
|
Kumar, Rahul;Kumar, Rahul;EmitaYulia, H;Hapsari, EmitaYulia;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil Kumar, T; |
| 亞洲大學 |
2013-10 |
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
|
Ankit Kumar;Emita Yulia;Emita Yulia Hapsari;Vasanth Kuma;Vasanth Kumar;Aryadeep Mri;Aryadeep Mrinal;許健;Gene Sheu;楊紹明;Shao-Ming Yang;Vivek Ningar |
| 亞洲大學 |
2013-10 |
Effect of Trench Depth and Trench Angle in a High Voltage Polyflanked-Super junction MOSFET
|
Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Nidhi, Karuna;Nidhi, Karuna;Agarw, Neelam;Agarwal, Neelam;Kumar, Ankit;Kumar, Ankit;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Mri, Aryadeep;Mrinal, Aryadeep |
| 亞洲大學 |
2013-10 |
Optimization of SiC Schottky Diode using Linear P for Edge Termination
|
Mri, Aryadeep;Aryadeep Mrinal, ;Kumar, Vijay;Vijay Kumar M P, ;Vivek N, ;Vivek N, ;Manjunatha, M;Manjunatha M, ;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2013-10 |
Process Integration of Best in Class Specific-on Resistance of 20V to 60V 0.18μm Bipolar CMOS DMOS Technology
|
Yulia, Emita;Hapsari, Emita Yulia;Kumar, Rahul;Kumar, Rahul;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil, T.V.;Anil, T.V. |
| 亞洲大學 |
2013-06 |
Ron Improvement with Duplex Conduction Channel
|
Manjunatha;Manjunatha;Vasanth;Vasanth;kumar, anil;kumar, anil;Kumar, Jaipal;Kumar, Jaipal;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;陳柏安;P.A.Chen |
| 亞洲大學 |
2013-06 |
Verification of Ruggedness and Failure in LDMOS
|
Chinmoy;Chinmoy;Shreyas;Shreyas;Kumar, Vijay;Kumar, Vijay;Neelam;Neelam;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-06 |
Investigation in characteristics of 1200V Vertical IGBT for different trench designs
|
Anil Kumar, P;Anil Kumar, P;Suresh, Vinay;Vinay Suresh, ;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-05 |
analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region
|
Tin, Hua Ting;Ting, Hua Ting;Guo, yu-feng;Guo, yu-feng;ying, yu;ying, yu;許健;Sheu, Gene |
| 亞洲大學 |
2013-02 |
Accurate equivalent circuit model of deep trench capacitor by numerical simulation and analytical calculation
|
Fathna, Ashif;Fathna, Ashif;kumar, Vikash;kumar, Vikash;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-02 |
Novel structure of deep trench capacitor with higher breakdown and higher capacitance density for Low Dropout Voltage regulator
|
Fathna, Ashif;Fathna, Ashif;kumar, Vikash;kumar, Vikash;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-01 |
An Analytical Model of Triple RESURF Device with Linear P?layer Doping Profile
|
Hua, Tingting;Hua, Tingting;Guo, Yufeng;Guo, Yufeng;Yu, Ying;Yu, Ying;許健;Sheu, Gene;Yao, Jiafei;Yao, Jiafei |
| 亞洲大學 |
2013-01 |
Novel Silicon-on-Insulator Lateral Power Device with Partial Oxide Pillars in the Drift Region
|
Yao, JiaFei;Yao, JiaFei;Guo, Yufeng;Guo, Yufeng;Hua, Tingting;Hua, Tingting;Huang, Shi;Huang, Shi;Zh, Changchun;Zhang, Changchun;Xia, Xiaojuan;Xia, Xiaojuan;許健;Sheu, Gene |
| 亞洲大學 |
2012.09 |
Characterization of NBTI by Evaluation of Hydrogen Amount in the Si/SiO2 Interface
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Characterization of NBTI by Evaluation of Hydrogen Amount in the Si/SiO2 Interface
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Failure Analysis of Power MOSFETs based on Multifinger Configuration under Unclamped Inductive
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Mechanism and Improvement of Breakdown Degradation Induced by Interface Charge in UHV
|
許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Study of energy capability and failure of LDMOSFET at different ambient temperatures
|
許健;Sheu, Gene;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Failure Analysis of Power MOSFETs based on Multi-finger Configuration under Unclamped Inductive Switching (UIS) Stress Condition
|
楊紹明;Yang, Shao-Ming;蔡宗叡;Tsai, Jung-Ruey;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Shifting Time Waveform Induced CMOS Latch Up in Bootstrapping Technique Applications
|
蔡宗叡;Tsai, Jung-Ruey;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Analysis of LDMOS for Effect of Fingers, Device-Width and Inductance on reverse recovery
|
蔡宗叡;Tsai, Jung-Ruey;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Optimization of ESD Protection Device Using SCR
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-08 |
Analysis of LDMOS for Effect of Finger and Device-width on Gate Feedback
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-08 |
Optimization of ESD Protection Device Using SCR Structure of a Novel STI-sided LDMOS with P-top
|
許健;Sheu, Gene |
| 亞洲大學 |
2012-08 |
Analysis of LDMOS for Effect of Finger and Device-width on Gate Feedback Charge
|
楊紹明;Yang, Shao-Ming;蔡宗叡;Tsai, Jung-Ruey;許健;Sheu, Gene |
| 亞洲大學 |
2012-08 |
Optimization of ESD Protection Device Using SCR Structure of a Novel STI-sided LDMOS with P-top Layer for 5 V Operating Voltage
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 國立高雄師範大學 |
2012-07-08 |
研究哈洛?品特主要劇作之抗爭模式
|
許健 |
| 亞洲大學 |
2012-07 |
A 2?D Analytical Model of SOI High?voltage Devices with Dual Conduction Layers
|
許健;Sheu, Gene |
| 亞洲大學 |
2012-06 |
Energy Capability of LDMOS as a Function of Ambient Temperature
|
許健;Sheu, Gene |
| 亞洲大學 |
2012-03 |
A New Methodology to Investigate the Effect of Stress and Bias on 2DEG and Drain Current of AlGaN/GaN Based Heterostructure
|
許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2012-03 |
A New Methodology to Investigate the Effect of Stress and Bias on 2DEG and Drain Current of AlGaN-GaN Based Heterostructure
|
許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2012-03 |
Optimization of nLDMOS ruggedness under Unclamped Inductive Switching (UIS) stress conditions by poly-gate extension
|
蔡宗叡;Tsai, Jung-Ruey;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2012-03 |
Analysis of LDMOS for Effect of Fingers, Device-Width and Inductance (Load) on Reverse Recovery
|
蔡宗叡;Tsai, Jung-Ruey;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2011-11 |
Design of Multiple RESURF LDMOS with P-top rings and STI regions in 65nm CMOS Technology
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;蔡宗叡;Tsai, Jung-Ruey |
| 亞洲大學 |
2011-11 |
Self-Consistent Electro-Thermo-Mechanical Analysis of AlN Passivation Effect on AlGaN/GaN HEMTs
|
許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2011-11 |
Development of ESD Robustness Enhancement of a Novel 800V LDMOS Multiple RESURF with Linear P-top Rings
|
蔡宗叡;Tsai, Jung-Ruey;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2011-08 |
Improvement of Electrical Characteristics in LDMOS by the Insertion of PBL
|
許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2011-08 |
Improvement of Electrical Characteristics in LDMOS by the Insertion of PBL and Gate Extended Field Plate Technologies
|
許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2011-08 |
Application of Multi-Lateral Double Diffused Field Ring in Ultrahigh-Voltage Device MOS Transistor Design
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey |
| 亞洲大學 |
2011-08 |
Effects of SiO2 passivation on AlGaN/GaN HEMT by self-consistent electro-thermal-mechanical simulation
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey |
| 亞洲大學 |
2011-07 |
An 800 Volts High Voltage Interconnection Level
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2011 |
A 2-dimensional mesh study using sentaurus simulator
|
許健;Sheu, Gene |
| 亞洲大學 |
2011 |
LDMOS Thermal SOA Investigation of a Novel 800V Multiple RESURF with
|
許健;Sheu, Gene |
| 亞洲大學 |
2011 |
A Novel 800V Multiple RESURF LDMOS Utilizing
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010.01 |
Analysis future and obstacle of solar building substance
|
陳秀宜;Chen, Shiu-Yi;鄭正豐;C.F.Cheng;許健;Sheu, Gene |
| 亞洲大學 |
2010-11 |
A 5V/200V SOI Device with a Vertically Linear Graded Drift Region
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey |
| 亞洲大學 |
2010-11 |
A 2D Analytical Model of Bulk-silicon Triple RESURF Devices
|
許健;Sheu, Gene |
| 亞洲大學 |
2010-11 |
A Novel 800V Multiple RESURF LDMOS Utilizing Linear P-top Rings
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
