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"許健"的相关文件
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| 亞洲大學 |
2016-05 |
EFFECT OF TIME AND TEMPERATURE ON EPITAXY GROWTH
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安南;Aanand;*;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;賴, 秋 仲;Sarwar, Syed;Imam, Syed Sarwar |
| 亞洲大學 |
2016-04 |
AN EXPERIMENTAL AND ANALYTICAL METHOD TO OBSERVE THE POLYSILICON NANOWIRE MOSFET THRESHOLD VOLTAGE
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;*;Aanand;Aanand;Syed;Imam, Syed Sarwar;范宗宸;Fan, Chung-Chen;Lu, Shao Wei;Lu, Shao Wei |
| 亞洲大學 |
2016-03 |
Effect of Time and Temperature on Epitaxy Growth
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Aanand;Aanand;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;*;賴秋仲;Lai, Ciou-Jhong;Syed;Imam, Syed Sarwar |
| 亞洲大學 |
2016 |
Silicon nanowire sensor for DNA biosensor applications
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李佳賢;Li, Chia-Hsien;*;Lu, Shao-Wei;Lu, Shao-Wei;Aanand;Aanand;Sarwar, Syed;Imam, Syed Sarwar;楊紹明;Yang, Shao-Ming;范宗宸;Fan, Chung-Chen;許健;Sheu, Gene |
| 亞洲大學 |
2015/06 |
International Symposium on the Physical and Failure Amalysis of Integrated Circuits
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楊紹明 ;Yang, Shao-Ming;許健; Sheu, Gene |
| 亞洲大學 |
2015-06 |
Reliability Analysis of Amorphous Silicon Thin-Film Transistors during Accelerated ESD stress
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蔡宗叡;TSAI, JUNG-RUEY;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;Cha, Ruey Dar;Chang, Ruey Dar;We, Ting Ting;Wen, Ting Ting |
| 亞洲大學 |
2015-03 |
High Voltage NLDMOS with Multiple-RESURF Structure to Achieve Improved On-resistance
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楊紹明;Yang, Shao-Ming;*; Hema, EP;Hema, EP;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;陳柏安;Chen, PA |
| 亞洲大學 |
2015-03 |
A HSPICE Macro Model for the ESD Behavior of Gate Grounded NMOS and Gate coupled NMOS
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楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;許健;Sheu, Gene;Mri, Aryadeep;Mrinal, Aryadeep;Md.Amanulla;Md.Amanullah;陳柏安;Chen, PA |
| 亞洲大學 |
2015-03 |
High Voltage NLDMOS with Multiple-RESURF Structure to Achieve Improved On-resistance
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楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;陳柏安;Chen, PA |
| 亞洲大學 |
2015-03 |
A HSPICE Macro Model for the ESD Behavior of Gate Grounded NMOS and Gate coupled NMOS
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楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;許健;Sheu, Gene;Mri, Aryadeep;Mrinal, Aryadeep;Md.Amanulla;Md.Amanullah;陳柏安;Chen, PA |
| 亞洲大學 |
2015-03 |
Negative e-beam resists using for nano-imprint lithography and silicone mold fabrication
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Anil Kumar, ;Anil Kumar, T.V.;Shy, S.L;Shy, S.L;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Chen, M.C.;Chen, M.C.;Hong, C.S.;Hong, C.S. |
| 亞洲大學 |
2014-05 |
Optimization of NLDMOS Structure for Higher breakdown voltage and lower on-resistance
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hema;hema;許健;Sheu, Gene;aryadeep;aryadeep;erry;erry;楊紹明;Yang, Shao-Ming;chen, PA;chen, PA |
| 亞洲大學 |
2014-05 |
A Study of Interstitial Effect on UMOS Performance
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Hema E. P;許健;Sheu, Gene;Aryadeep M;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2014-05 |
An Accurate Prediction for as-Implanted Doping Profile Calibration Using Different Ion Implantation
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Vivek;Vivek;pradahana;pradahana;許健;Sheu, Gene;王俊博;Subramaya;Subramaya;Amanullah;Amanullah;Sharma;Sharma;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2014-03 |
Investigation of Current Density and Hotspot Temperature Distribution Effects on P-channel LDMOSFET Unclamped Inductive Switching ;UIS) Test
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Kur, Erry Dwi;Kurniawan, Erry Dwi;Fra, Antonius; Ankit Kuma; Ankit Kumar;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2014-03 |
High Performance Gallium Nitride GAA Nanowire with 7nm diameter for Ultralow-Power Logic Applications
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Anil Kumar, T;Ch, Min-Cheng;Chen, Min-Cheng;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2014-03 |
A Low-cost 900V rated Multiple RESURF LDMOS Ultrahigh-Voltage Device MOS Transistor Design without EPI Layer
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Anil Kumar, T;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;Chen, P.A;Chen, P.A |
| 亞洲大學 |
2014-01 |
Optimization of SiC Schottky Diode using Linear P-top for Edge
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Mri, Aryadeep;Mrinal, Aryadeep;Kumar, Vijay;Vivek N, Man;Vivek N, Manjunatha M;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2014-01 |
A Novel Ultra High Voltage Sidewall Implant Super Junction MOSFET Using Arsenic Implantation under Trench Bottom
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Kumar, Rahul;Kumar, Rahul;EmitaYulia, H;Hapsari, EmitaYulia;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming; Anil Kumar; Anil Kumar TV |
| 亞洲大學 |
201310 |
Process Integration of Best in Class Specific-on Resistance of 20V to 60V 0.18μm Bipolar CMOS DMOS Technology
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Yulia, Emita;Hapsari, Emita Yulia;Kumar, Rahul;Kumar, Rahul;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil, T.V.;Anil, T.V. |
| 亞洲大學 |
201310 |
Optimization of SiC Schottky Diode using Linear P for Edge Termination
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Mri, Aryadeep;Mrinal, Aryadeep;Kumar, Vijay;Vivek, N;Vivek, N;Manjunatha, M;Manjunatha, M;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
201310 |
Effect of Trench Depth and Trench Angle in a High Voltage Polyflanked-Super junction MOSFET
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Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Nidhi, Karuna;Nidhi, Karuna;Agarw, Neelam;Agarwal, Neelam;Kumar, Ankit;Kumar, Ankit;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Mri, Aryadeep;Mrinal, Aryadeep |
| 亞洲大學 |
201310 |
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
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Kumar, Ankit;Kumar, Ankit;Yulia, Emita;Hapsari, Emita Yulia;Kuma, Vasanth;Kumar, Vasanth;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Ningar, Vivek;Ningaraju, Vivek |
| 亞洲大學 |
201310 |
A Novel Ultra High Voltage Sidewall Implant Super Junction MOSFET Using Arsenic Implantation under Trench Bottom
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Kumar, Rahul;Kumar, Rahul;EmitaYulia, H;Hapsari, EmitaYulia;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil Kumar, T; |
| 亞洲大學 |
201306 |
Effects of Antimony and Arsenic Ion Implantation on High Performance of Ultra High Voltage Device
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Kum, Vasantha;Manjunatha, M;Manjunatha, M;Suresh, Vinay;Suresh, Vinay;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;陳柏安;Chen, P A |
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