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"許健"的相关文件
显示项目 11-60 / 107 (共3页)
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| 亞洲大學 |
2015-03 |
Negative e-beam resists using for nano-imprint lithography and silicone mold fabrication
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Anil Kumar, ;Anil Kumar, T.V.;Shy, S.L;Shy, S.L;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Chen, M.C.;Chen, M.C.;Hong, C.S.;Hong, C.S. |
| 亞洲大學 |
2014-05 |
Optimization of NLDMOS Structure for Higher breakdown voltage and lower on-resistance
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hema;hema;許健;Sheu, Gene;aryadeep;aryadeep;erry;erry;楊紹明;Yang, Shao-Ming;chen, PA;chen, PA |
| 亞洲大學 |
2014-05 |
A Study of Interstitial Effect on UMOS Performance
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Hema E. P;許健;Sheu, Gene;Aryadeep M;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2014-05 |
An Accurate Prediction for as-Implanted Doping Profile Calibration Using Different Ion Implantation
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Vivek;Vivek;pradahana;pradahana;許健;Sheu, Gene;王俊博;Subramaya;Subramaya;Amanullah;Amanullah;Sharma;Sharma;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2014-03 |
Investigation of Current Density and Hotspot Temperature Distribution Effects on P-channel LDMOSFET Unclamped Inductive Switching ;UIS) Test
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Kur, Erry Dwi;Kurniawan, Erry Dwi;Fra, Antonius; Ankit Kuma; Ankit Kumar;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2014-03 |
High Performance Gallium Nitride GAA Nanowire with 7nm diameter for Ultralow-Power Logic Applications
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Anil Kumar, T;Ch, Min-Cheng;Chen, Min-Cheng;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2014-03 |
A Low-cost 900V rated Multiple RESURF LDMOS Ultrahigh-Voltage Device MOS Transistor Design without EPI Layer
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Anil Kumar, T;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;Chen, P.A;Chen, P.A |
| 亞洲大學 |
2014-01 |
Optimization of SiC Schottky Diode using Linear P-top for Edge
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Mri, Aryadeep;Mrinal, Aryadeep;Kumar, Vijay;Vivek N, Man;Vivek N, Manjunatha M;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2014-01 |
A Novel Ultra High Voltage Sidewall Implant Super Junction MOSFET Using Arsenic Implantation under Trench Bottom
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Kumar, Rahul;Kumar, Rahul;EmitaYulia, H;Hapsari, EmitaYulia;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming; Anil Kumar; Anil Kumar TV |
| 亞洲大學 |
201310 |
Process Integration of Best in Class Specific-on Resistance of 20V to 60V 0.18μm Bipolar CMOS DMOS Technology
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Yulia, Emita;Hapsari, Emita Yulia;Kumar, Rahul;Kumar, Rahul;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil, T.V.;Anil, T.V. |
| 亞洲大學 |
201310 |
Optimization of SiC Schottky Diode using Linear P for Edge Termination
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Mri, Aryadeep;Mrinal, Aryadeep;Kumar, Vijay;Vivek, N;Vivek, N;Manjunatha, M;Manjunatha, M;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
201310 |
Effect of Trench Depth and Trench Angle in a High Voltage Polyflanked-Super junction MOSFET
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Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Nidhi, Karuna;Nidhi, Karuna;Agarw, Neelam;Agarwal, Neelam;Kumar, Ankit;Kumar, Ankit;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Mri, Aryadeep;Mrinal, Aryadeep |
| 亞洲大學 |
201310 |
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
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Kumar, Ankit;Kumar, Ankit;Yulia, Emita;Hapsari, Emita Yulia;Kuma, Vasanth;Kumar, Vasanth;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Ningar, Vivek;Ningaraju, Vivek |
| 亞洲大學 |
201310 |
A Novel Ultra High Voltage Sidewall Implant Super Junction MOSFET Using Arsenic Implantation under Trench Bottom
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Kumar, Rahul;Kumar, Rahul;EmitaYulia, H;Hapsari, EmitaYulia;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil Kumar, T; |
| 亞洲大學 |
201306 |
Effects of Antimony and Arsenic Ion Implantation on High Performance of Ultra High Voltage Device
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Kum, Vasantha;Manjunatha, M;Manjunatha, M;Suresh, Vinay;Suresh, Vinay;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;陳柏安;Chen, P A |
| 亞洲大學 |
201306 |
Investigation of Substrate Resistance and Inductance on Deep Trench Capacitor for RF Application
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kumar, Vikash;kumar, Vikash;Aminul, Ashif;Aminulloh, Ashif;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
201306 |
P-type Shallow Junction as-Implanted Profile Prediction Using Kinetic Monte Carlo Simulation
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Fra, Antonius;Kur, Erry Dwi;Kurniawan, Erry Dwi;Manjunatha, M;Manjunatha, M.;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
201306 |
Ron Improvement with Duplex Conduction Channel
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Manjunatha;Manjunatha;Vasanth;Vasanth;kumar, anil;kumar, anil;Kumar, Jaipal;Kumar, Jaipal;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;陳柏安;P.A.Chen |
| 亞洲大學 |
201306 |
Unclamped Inductive Switching Stress Failure Mechanism of LDMOS
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Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Khau, Chinmoy;Khaund, Chinmoy;Agarw, Neelam;Agarwal, Neelam;Nidhi, Karuna;Nidhi, Karuna;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
201306 |
Verification of Ruggedness and Failure in LDMOS
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Chinmoy;Chinmoy;Shreyas;Shreyas;Kumar, Vijay;Kumar, Vijay;Neelam;Neelam;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
201302 |
Accurate equivalent circuit model of deep trench capacitor by numerical simulation and analytical calculation
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Fathna, Ashif;Fathna, Ashif;kumar, Vikash;kumar, Vikash;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
201302 |
Novel structure of deep trench capacitor with higher breakdown and higher capacitance density for Low Dropout Voltage regulator
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Fathna, Ashif;Fathna, Ashif;kumar, Vikash;kumar, Vikash;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-10 |
A Novel Ultra High Voltage Sidewall Implant Super Junction MOSFET Using Arsenic Implantation under Trench Bottom
|
Kumar, Rahul;Kumar, Rahul;EmitaYulia, H;Hapsari, EmitaYulia;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil Kumar, T; |
| 亞洲大學 |
2013-10 |
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
|
Ankit Kumar;Emita Yulia;Emita Yulia Hapsari;Vasanth Kuma;Vasanth Kumar;Aryadeep Mri;Aryadeep Mrinal;許健;Gene Sheu;楊紹明;Shao-Ming Yang;Vivek Ningar |
| 亞洲大學 |
2013-10 |
Effect of Trench Depth and Trench Angle in a High Voltage Polyflanked-Super junction MOSFET
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Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Nidhi, Karuna;Nidhi, Karuna;Agarw, Neelam;Agarwal, Neelam;Kumar, Ankit;Kumar, Ankit;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Mri, Aryadeep;Mrinal, Aryadeep |
| 亞洲大學 |
2013-10 |
Optimization of SiC Schottky Diode using Linear P for Edge Termination
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Mri, Aryadeep;Aryadeep Mrinal, ;Kumar, Vijay;Vijay Kumar M P, ;Vivek N, ;Vivek N, ;Manjunatha, M;Manjunatha M, ;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2013-10 |
Process Integration of Best in Class Specific-on Resistance of 20V to 60V 0.18μm Bipolar CMOS DMOS Technology
|
Yulia, Emita;Hapsari, Emita Yulia;Kumar, Rahul;Kumar, Rahul;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil, T.V.;Anil, T.V. |
| 亞洲大學 |
2013-06 |
Ron Improvement with Duplex Conduction Channel
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Manjunatha;Manjunatha;Vasanth;Vasanth;kumar, anil;kumar, anil;Kumar, Jaipal;Kumar, Jaipal;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;陳柏安;P.A.Chen |
| 亞洲大學 |
2013-06 |
Verification of Ruggedness and Failure in LDMOS
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Chinmoy;Chinmoy;Shreyas;Shreyas;Kumar, Vijay;Kumar, Vijay;Neelam;Neelam;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-06 |
Investigation in characteristics of 1200V Vertical IGBT for different trench designs
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Anil Kumar, P;Anil Kumar, P;Suresh, Vinay;Vinay Suresh, ;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-05 |
analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region
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Tin, Hua Ting;Ting, Hua Ting;Guo, yu-feng;Guo, yu-feng;ying, yu;ying, yu;許健;Sheu, Gene |
| 亞洲大學 |
2013-02 |
Accurate equivalent circuit model of deep trench capacitor by numerical simulation and analytical calculation
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Fathna, Ashif;Fathna, Ashif;kumar, Vikash;kumar, Vikash;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-02 |
Novel structure of deep trench capacitor with higher breakdown and higher capacitance density for Low Dropout Voltage regulator
|
Fathna, Ashif;Fathna, Ashif;kumar, Vikash;kumar, Vikash;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2013-01 |
An Analytical Model of Triple RESURF Device with Linear P?layer Doping Profile
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Hua, Tingting;Hua, Tingting;Guo, Yufeng;Guo, Yufeng;Yu, Ying;Yu, Ying;許健;Sheu, Gene;Yao, Jiafei;Yao, Jiafei |
| 亞洲大學 |
2013-01 |
Novel Silicon-on-Insulator Lateral Power Device with Partial Oxide Pillars in the Drift Region
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Yao, JiaFei;Yao, JiaFei;Guo, Yufeng;Guo, Yufeng;Hua, Tingting;Hua, Tingting;Huang, Shi;Huang, Shi;Zh, Changchun;Zhang, Changchun;Xia, Xiaojuan;Xia, Xiaojuan;許健;Sheu, Gene |
| 亞洲大學 |
2012.09 |
Characterization of NBTI by Evaluation of Hydrogen Amount in the Si/SiO2 Interface
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楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Characterization of NBTI by Evaluation of Hydrogen Amount in the Si/SiO2 Interface
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楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Failure Analysis of Power MOSFETs based on Multifinger Configuration under Unclamped Inductive
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楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Mechanism and Improvement of Breakdown Degradation Induced by Interface Charge in UHV
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許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Study of energy capability and failure of LDMOSFET at different ambient temperatures
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許健;Sheu, Gene;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Failure Analysis of Power MOSFETs based on Multi-finger Configuration under Unclamped Inductive Switching (UIS) Stress Condition
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楊紹明;Yang, Shao-Ming;蔡宗叡;Tsai, Jung-Ruey;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Shifting Time Waveform Induced CMOS Latch Up in Bootstrapping Technique Applications
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蔡宗叡;Tsai, Jung-Ruey;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Analysis of LDMOS for Effect of Fingers, Device-Width and Inductance on reverse recovery
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蔡宗叡;Tsai, Jung-Ruey;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-09 |
Optimization of ESD Protection Device Using SCR
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楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-08 |
Analysis of LDMOS for Effect of Finger and Device-width on Gate Feedback
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楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2012-08 |
Optimization of ESD Protection Device Using SCR Structure of a Novel STI-sided LDMOS with P-top
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許健;Sheu, Gene |
| 亞洲大學 |
2012-08 |
Analysis of LDMOS for Effect of Finger and Device-width on Gate Feedback Charge
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楊紹明;Yang, Shao-Ming;蔡宗叡;Tsai, Jung-Ruey;許健;Sheu, Gene |
| 亞洲大學 |
2012-08 |
Optimization of ESD Protection Device Using SCR Structure of a Novel STI-sided LDMOS with P-top Layer for 5 V Operating Voltage
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 國立高雄師範大學 |
2012-07-08 |
研究哈洛?品特主要劇作之抗爭模式
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許健 |
| 亞洲大學 |
2012-07 |
A 2?D Analytical Model of SOI High?voltage Devices with Dual Conduction Layers
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許健;Sheu, Gene |
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