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"謝曜式"的相关文件

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机构	日期	题名	作者
中華大學	2006	VLSI Implementation of 2-D Discrete Cosine Transform Architecture Based on CORDIC Rotation,	謝曜式; Shieh, Yaw-Shih
中華大學	2006	Cost-Effective Architectures for 2-D Forward and Inverse Discrete Cosine Transform Architecture	謝曜式; Shieh, Yaw-Shih
中華大學	2006	A High-Efficient and Cost-Effective LCD Signal Processor	謝曜式; Shieh, Yaw-Shih
中華大學	2006	Memory-Efficiency Multiplierless VLSI Architecture for 2-D DWT Using 9/7 Wavelet Filter	謝曜式; Shieh, Yaw-Shih
中華大學	2006	The Closed-Loop Control of the Dual-Output Buck-Boost Converters with Structure of Single-Inductor Boost Converter	謝曜式; Shieh, Yaw-Shih
中華大學	2006	High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform Using 5/3 Wavelet Filter	謝曜式; Shieh, Yaw-Shih
中華大學	2006	VLSI Implementation of a High-Efficient and Cost-Effective LCD Singal Processor,	謝曜式; Shieh, Yaw-Shih
中華大學	2006	The Closed-Loop Control for Dual-Output Boost Converter with Single inductor	謝曜式; Shieh, Yaw-Shih
中華大學	2006	Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation,	謝曜式; Shieh, Yaw-Shih
中華大學	2005	FPGA Implementation of Image Scalar for LCD Monitor and TV Controller	謝曜式; Shieh, Yaw-Shih
中華大學	2005	Area, Power and Throughput Trade-Offs for 2-D Inverse Discrete Wavelet Transform Architectures Using Direct Form	謝曜式; Shieh, Yaw-Shih
中華大學	2005	Area and Throughput Trade-offs in The Design of Pipelined 2-D Discrete Wavelet Transform Architectures	謝曜式; Shieh, Yaw-Shih
中華大學	2005	A Full Band Low Power Low Phase Noise LC VCO for IEEE 802.11a	謝曜式; Shieh, Yaw-Shih
中華大學	2005	Design and Implementation of LCD Monitor/TV Signal Processor	謝曜式; Shieh, Yaw-Shih
中華大學	2005	A Free Jitter Phase Frequency Detector with Negligible Dead Zone	謝曜式; Shieh, Yaw-Shih
中華大學	2005	Design and Analysis of Pipelined Discrete Wavelet Transform Architectures	謝曜式; Shieh, Yaw-Shih
中華大學	2005	VLSI Implementation of a CORDIC-Based 2-D Discrete Cosine Transform and Its Inverse	謝曜式; Shieh, Yaw-Shih
中華大學	2005	Hardware Implementation of Fast 3-D Rotation Using Double Rotation CORDIC Algorithm in Graphic Engine	謝曜式; Shieh, Yaw-Shih
中華大學	2005	Design and Analysis of a High-Speed Sine/Cosine Generator in OFDM System	謝曜式; Shieh, Yaw-Shih
中華大學	2005	VLSI Implementation of a Memory-Efficient and High-Speed Split-Radix FFT/IFFT Processor for Wireless LAN	謝曜式; Shieh, Yaw-Shih
中華大學	2005	VLSI Implementation of Pipelined Architectures for 2-D Discrete Wavelet Transform and Its Inversion	謝曜式; Shieh, Yaw-Shih
中華大學	2005	A High-Speed /Ultra Low-Power Architecture for Two-Dimensional Discrete Wavelet Transform	謝曜式; Shieh, Yaw-Shih
中華大學	2005	Dual Output Boost Converter Using Single Inductor	謝曜式; Shieh, Yaw-Shih
中華大學	2005	A High Speed and Low Dead Zone PFD with Delay Circuits	謝曜式; Shieh, Yaw-Shih
中華大學	2005	A igh-Speed/Low-Power Architecture for Two-Dimensional Inverse Discrete Wavelet Transform With Multiplierless Operation	謝曜式; Shieh, Yaw-Shih

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