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"謝曜式"???jsp.browse.items-by-author.description???
Showing items 11-35 of 75 (3 Page(s) Totally) 1 2 3 > >> View [10|25|50] records per page
中華大學 |
2012 |
A Unified Algorithm for Subband-Based Discrete Cosine Transform
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2012 |
Haar-Wavelet-Based Just Noticeable Distortion Model for Transparent Watermark
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2011 |
FPGA Implementation of High Performance DCT/IDCT Processor
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2011 |
Wavelet Based Just Noticeable Distortion Model for Transparent Watermarking
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2010 |
A Novel VLSI Linear Array for Discrete Cosine Transform and Its Inverse
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2010 |
A Novel VLSI Linear Array for 2-D DCT/IDCT
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2010 |
An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2010 |
A Novel Linear Array for Discrete Cosine Transform
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2009 |
The Fast DCT and IDCT Algorithm by Subband Decomposition of signal
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2009 |
一種快速正弦與餘弦函數產生器
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2008 |
A Superior Algorithm for Resizing Images by using the Subband DCT
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2007 |
A Fast Algorithm for Resizing Images in the DCT Domain
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
VLSI Implementation of Memory-Efficiency Multiplierless DCT and IDCT Processors
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
A High-Efficient Line-Based Architecture for 2-D Discrete Wavelet Transform Based on Lifting Scheme Using 9/7 Wavelet Filters
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
A High-Efficient Line-Based Architecture for 2-D Lifting-Based DWT Using 9/7 Wavelet Filters
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
A High-Efficient Image Scalar Algorithm for LCD Signal Processor
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
VLSI Implementation of A High-Efficient Image Scalar Algorithm for LCD Signal Processor
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
High-Speed and Low-Power Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-Tap Daubechies Filters
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
An Efficient CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphics Rendering
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
台灣科技產業結構性改變與管理之變遷
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
A High-Throughput and Memory-Efficiency 2-D DCT Architecture Based on CORDIC Rotation
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謝曜式; Shieh, Yaw-Shih |
中華大學 |
2006 |
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering
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謝曜式; Shieh, Yaw-Shih |
Showing items 11-35 of 75 (3 Page(s) Totally) 1 2 3 > >> View [10|25|50] records per page
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