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"謝曜式"
Showing items 46-55 of 75 (8 Page(s) Totally)
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| 中華大學 |
2006 |
VLSI Implementation of 2-D Discrete Cosine Transform Architecture Based on CORDIC Rotation,
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
Cost-Effective Architectures for 2-D Forward and Inverse Discrete Cosine Transform Architecture
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
A High-Efficient and Cost-Effective LCD Signal Processor
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
Memory-Efficiency Multiplierless VLSI Architecture for 2-D DWT Using 9/7 Wavelet Filter
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
The Closed-Loop Control of the Dual-Output Buck-Boost Converters with Structure of Single-Inductor Boost Converter
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform Using 5/3 Wavelet Filter
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
VLSI Implementation of a High-Efficient and Cost-Effective LCD Singal Processor,
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
The Closed-Loop Control for Dual-Output Boost Converter with Single inductor
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation,
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謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2005 |
FPGA Implementation of Image Scalar for LCD Monitor and TV Controller
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謝曜式; Shieh, Yaw-Shih |
Showing items 46-55 of 75 (8 Page(s) Totally)
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