English  |  正體中文  |  简体中文  |  Total items :0  
Visitors :  52078758    Online Users :  1054
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
About TAIR

Browse By

News

Copyright

Related Links

"陳永源"

Return to Browse by Author
Sorting by Title Sort by Date

Showing items 11-35 of 53  (3 Page(s) Totally)
1 2 3 > >>
View [10|25|50] records per page

Institution Date Title Author
中華大學 2008 An Estimation Model of Vulnerability for Embedded Microprocessors 陳永源; Chen, Yung-Yuan
中華大學 2008 System-Bus Fault Injection Framework in SystemC Design Platform 陳永源; Chen, Yung-Yuan
中華大學 2008 Datapath Error Detection with No Detection Latency for High-Performance Microprocessors 陳永源; Chen, Yung-Yuan
中華大學 2008 行為層高效能處理器的容錯設計及快速驗證與容錯能力分析(III) 陳永源
中華大學 2008 Datapath Error Detection with Hybrid Detection Approach for High-Performance Microprocessors 陳永源; Chen, Yung-Yuan
亞洲大學 2007-12-20 單層多對節點連結演算法 詹景裕;劉萬榮;郭芳誠;陳永源
國立中山大學 2007-07-17 影響企業員工採用PDA行動巡補系統因素之研究-以統一速邁為例 陳永源
中華大學 2007 Fault-Tolerant Verification Platform for Systems Modeled at High Level of Abstraction 陳永源; Chen, Yung-Yuan
中華大學 2007 System-Level Fault Injection in SystemC Design Platform 陳永源; Chen, Yung-Yuan
中華大學 2007 Experimental Assessment of Fault Coverage for Fault-Tolerant High-Performance Processors 陳永源; Chen, Yung-Yuan
中華大學 2007 A Comparison of Fault Injection Experiments under Different Verification Environments 陳永源; Chen, Yung-Yuan
中華大學 2007 A New Concurrent Detection of Control Flow Errors Based on DCT Technique 陳永源; Chen, Yung-Yuan
中華大學 2007 行為層高效能處理器的容錯設計及快速驗證與容錯能力分析(II) 陳永源
中華大學 2006 Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors 陳永源; Chen, Yung-Yuan
中華大學 2006 Fault-Tolerant VLIW Processor Design and Error Coverage Analysis 陳永源; Chen, Yung-Yuan
中華大學 2006 A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture 陳永源; Chen, Yung-Yuan
中華大學 2006 行為層高效能處理器的容錯設計及快速驗證與容錯能力分析(I) 陳永源
中華大學 2005 Embedding Watchdog Processor Scheme in VLIW Architecture 陳永源; Chen, Yung-Yuan
中華大學 2005 Incorporating Fault-Tolerant Features in VLIW Processors 陳永源; Chen, Yung-Yuan
中華大學 2005 Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring 陳永源; Chen, Yung-Yuan
中華大學 2005 Signature-monitoring technique based on instruction-bit grouping 陳永源; Chen, Yung-Yuan
中華大學 2005 針對VLIW處理器提出一有效的容錯設計架構 陳永源
中華大學 2004 VLIW Processor with Embedded Watchdog Processor for Control Flow Error Detection 陳永源; Chen, Yung-Yuan
中華大學 2004 Power-Effective Fault-Tolerant VLIW Processors 陳永源; Chen, Yung-Yuan
中華大學 2004 A New Signature-Monitoring Technique Based on Instruction Bit Grouping 陳永源; Chen, Yung-Yuan

Showing items 11-35 of 53  (3 Page(s) Totally)
1 2 3 > >>
View [10|25|50] records per page