|
English
|
正體中文
|
简体中文
|
Total items :2831195
|
|
Visitors :
33227230
Online Users :
1025
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"顏金泰"
Showing items 41-65 of 100 (4 Page(s) Totally)
<< < 1 2 3 4 > >>
View [10|25|50] records per page
| 中華大學 |
2009 |
考量溫度限制之三維晶片版面規劃與擺置系統開發
|
顏金泰 |
| 中華大學 |
2009 |
計算機組織與結構概論
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment and Path Reconstruction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Constrained Yield-driven Redundant Via Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Thermal-Driven White Space Redistribution for Block-Level Floorplans
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Electromigration-aware Rectilinear Steiner Tree Construction for Analog Circuits
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Simultaneous Assignment of Power Pads and Wires for Reliability-Driven Hierarchical Power Quad-Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Multi-Layer Steiner Tree Construction with Obstacle Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Packing-Driven Sliceable Transformation for 3D Floorplan Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Noise-Aware Multiple-Voltage Assignment for gate-Level Power Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Steiner Tree Construction for Three-Dimensional ICs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Flexible Escape Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Constrained Redundant Via Insertion for Yield Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Top-Down-Based Timing-Driven Steiner Tree Construction with Wire Sizing and Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis for Signal Integrity
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Feasible Assignment of Wire-Bonding Power Pads in Hierarchical Power Quad-Grids for Signal Integrity
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Routability-Driven Track Routing for Coupling Capacitance Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
具有反面晶片技術的晶片與封裝共構繞線發展(I)
|
顏金泰 |
| 中華大學 |
2006 |
Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis
|
顏金泰; YAN, JIN-TAI |
Showing items 41-65 of 100 (4 Page(s) Totally)
<< < 1 2 3 4 > >>
View [10|25|50] records per page
|
