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"顏金泰"
Showing items 46-70 of 100 (4 Page(s) Totally)
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| 中華大學 |
2008 |
Electromigration-aware Rectilinear Steiner Tree Construction for Analog Circuits
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Simultaneous Assignment of Power Pads and Wires for Reliability-Driven Hierarchical Power Quad-Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Multi-Layer Steiner Tree Construction with Obstacle Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Packing-Driven Sliceable Transformation for 3D Floorplan Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Noise-Aware Multiple-Voltage Assignment for gate-Level Power Optimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Steiner Tree Construction for Three-Dimensional ICs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Flexible Escape Routing for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Constrained Redundant Via Insertion for Yield Optimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Top-Down-Based Timing-Driven Steiner Tree Construction with Wire Sizing and Buffer Insertion
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis for Signal Integrity
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Feasible Assignment of Wire-Bonding Power Pads in Hierarchical Power Quad-Grids for Signal Integrity
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Routability-Driven Track Routing for Coupling Capacitance Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
具有反面晶片技術的晶片與封裝共構繞線發展(I)
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顏金泰 |
| 中華大學 |
2006 |
Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Optimal Network Analysis in Hierarchical Power Quad-Grids
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Width and Timing-Constrained Wire Sizing for Critical Area Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Multilevel Timing-Constrained Full-Chip Routing in Hierarchical Quad-Grid Model
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Floorplan-Aware Decoupling Capacitance Budgeting on Equivalent Circuit Model
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Area-Driven White Space Distribution for Detailed Floorplan Design
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顏金泰; YAN, JIN-TAI |
Showing items 46-70 of 100 (4 Page(s) Totally)
<< < 1 2 3 4 > >>
View [10|25|50] records per page
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