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"顏金泰"

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Showing items 51-75 of 100 (4 Page(s) Totally)
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Institution	Date	Title	Author
中華大學	2008	Timing-Driven Steiner Tree Construction for Three-Dimensional ICs	顏金泰; YAN, JIN-TAI
中華大學	2008	Flexible Escape Routing for Flip-Chip Designs	顏金泰; YAN, JIN-TAI
中華大學	2007	Timing-Constrained Redundant Via Insertion for Yield Optimization	顏金泰; YAN, JIN-TAI
中華大學	2007	Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance	顏金泰; YAN, JIN-TAI
中華大學	2007	Top-Down-Based Timing-Driven Steiner Tree Construction with Wire Sizing and Buffer Insertion	顏金泰; YAN, JIN-TAI
中華大學	2007	Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis for Signal Integrity	顏金泰; YAN, JIN-TAI
中華大學	2007	Feasible Assignment of Wire-Bonding Power Pads in Hierarchical Power Quad-Grids for Signal Integrity	顏金泰; YAN, JIN-TAI
中華大學	2007	Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity	顏金泰; YAN, JIN-TAI
中華大學	2007	Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2007	Routability-Driven Track Routing for Coupling Capacitance Reduction	顏金泰; YAN, JIN-TAI
中華大學	2007	具有反面晶片技術的晶片與封裝共構繞線發展(I)	顏金泰
中華大學	2006	Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning	顏金泰; YAN, JIN-TAI
中華大學	2006	Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2006	Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment	顏金泰; YAN, JIN-TAI
中華大學	2006	Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis	顏金泰; YAN, JIN-TAI
中華大學	2006	Optimal Network Analysis in Hierarchical Power Quad-Grids	顏金泰; YAN, JIN-TAI
中華大學	2006	Width and Timing-Constrained Wire Sizing for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2006	Multilevel Timing-Constrained Full-Chip Routing in Hierarchical Quad-Grid Model	顏金泰; YAN, JIN-TAI
中華大學	2006	Floorplan-Aware Decoupling Capacitance Budgeting on Equivalent Circuit Model	顏金泰; YAN, JIN-TAI
中華大學	2006	Area-Driven White Space Distribution for Detailed Floorplan Design	顏金泰; YAN, JIN-TAI
中華大學	2006	OPC-Aware Routing Reconstruction for OPE Reduction	顏金泰; YAN, JIN-TAI
中華大學	2006	Timing-Constrained Yield-Driven Wire Sizing for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2006	可避免干擾雜訊的SOC晶片繞線系統的開發	顏金泰
中華大學	2006	Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2005	Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization	顏金泰; YAN, JIN-TAI

Showing items 51-75 of 100 (4 Page(s) Totally)
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