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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"顏金泰"的相關文件
顯示項目 1-25 / 100 (共4頁)
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每頁顯示[10|25|50]項目
| 國立交通大學 |
2014-12-12T02:14:17Z |
在聚集晶元佈局上K-方電路分割,擺置改良,區域定義和繞線順序設計之設計
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顏金泰; Yan, Jin Tai; 蕭培墉; Xiao, Pei Yong |
| 國立交通大學 |
2014-12-12T02:06:45Z |
一個(M+1)位元迴饋分割式通訊協定
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顏金泰; YAN,JIN-TAI; 簡榮宏; JIAN,RONG-HONG |
| 中華大學 |
2013 |
Routability-Constrained Multi-Bit Flip-Flop Construction for Clock Power Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Timing-Constrained Replacement Using Spare Cells for Design Changes
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Resource-Constrained Link Insertion for Delay Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Utilization of Multi-Bit Flip-Flops for Clock Power Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Top-Down-Based Symmetrical Buffered Clock Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Direction-Constrained Layer Assignment for Rectangle Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Timing-Constrained I/O Buffer Placement for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-Aware Length-Matching Bus Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Pre-Assignment RDL Routing via Extraction of Maximal Net Sequence
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Simultaneous Escape Routing Based on Routability-Driven Net Ordering
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
考量不同佈局需求的單層繞線系統開發
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顏金泰 |
| 中華大學 |
2010 |
Thermal Via Planning for Temperature Reduction in 3D ICs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Low-Cost Low-Power Bypassing-Based Multiplier Design
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-Driven Flip-Flop Merging Process for Clock Power Reduction
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顏金泰; YAN, JIN-TAI |
顯示項目 1-25 / 100 (共4頁)
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每頁顯示[10|25|50]項目
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