臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
中華大學	2011	Timing-Constrained I/O Buffer Placement for Flip-Chip Designs	顏金泰; YAN, JIN-TAI
中華大學	2011	New Optimal Layer Assignment for Bus-Oriented Escape Routing	顏金泰; YAN, JIN-TAI
中華大學	2011	Obstacle-Aware Length-Matching Bus Routing	顏金泰; YAN, JIN-TAI
中華大學	2011	Pre-Assignment RDL Routing via Extraction of Maximal Net Sequence	顏金泰; YAN, JIN-TAI
中華大學	2011	Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance	顏金泰; YAN, JIN-TAI
中華大學	2011	Simultaneous Escape Routing Based on Routability-Driven Net Ordering	顏金泰; YAN, JIN-TAI
中華大學	2011	考量不同佈局需求的單層繞線系統開發	顏金泰
中華大學	2010	Thermal Via Planning for Temperature Reduction in 3D ICs	顏金泰; YAN, JIN-TAI
中華大學	2010	Low-Cost Low-Power Bypassing-Based Multiplier Design	顏金泰; YAN, JIN-TAI
中華大學	2010	Routability-Driven Flip-Flop Merging Process for Clock Power Reduction	顏金泰; YAN, JIN-TAI
中華大學	2010	Routability-driven partitioning-based IO assignment for flip-chip designs	顏金泰; YAN, JIN-TAI
中華大學	2010	Routability-Driven RDL Routing with Pin Reassignment	顏金泰; YAN, JIN-TAI
中華大學	2010	Two-Sided Single-Detour Untangling for Bus Routing	顏金泰; YAN, JIN-TAI
中華大學	2010	Ordered Escape Routing via Routability-Driven Pin Assignment	顏金泰; YAN, JIN-TAI
中華大學	2010	Width-constrained Wire Sizing for Non-tree Interconnections	顏金泰; YAN, JIN-TAI
中華大學	2010	Obstacle-Aware Longest Path using Rectangular Pattern Detouring in Routing Grids	顏金泰; YAN, JIN-TAI
中華大學	2010	Resource-Constrained Timing-Driven Link Insertion for Critical Delay Reduction	顏金泰; YAN, JIN-TAI
中華大學	2010	在高密度印刷電路板設計下的匯流排導向繞線系統開發	顏金泰
中華大學	2009	Optimal Transformation of Non-tree Topologies for Timing Analysis	顏金泰; YAN, JIN-TAI
中華大學	2009	Low-Power Multiplier Design with Row and Column Bypassing	顏金泰; YAN, JIN-TAI
中華大學	2009	RDL Pre-assignment Routing for Flip-Chip Designs	顏金泰; YAN, JIN-TAI
中華大學	2009	IO Connection Assignment and RDL Routing for Flip-Chip Designs	顏金泰; YAN, JIN-TAI
中華大學	2009	Construction of Constrained Multi-Bit Flip-Flops for Clock Power Reduction	顏金泰; YAN, JIN-TAI
中華大學	2009	Accurate Transformation-Based Timing Analysis for RC Non-tree Circuits	顏金泰; YAN, JIN-TAI
中華大學	2009	Redundant Wire Insertion for Yield Improvement	顏金泰; YAN, JIN-TAI

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