臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
中華大學	2006	Optimal Network Analysis in Hierarchical Power Quad-Grids	顏金泰; YAN, JIN-TAI
中華大學	2006	Width and Timing-Constrained Wire Sizing for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2006	Multilevel Timing-Constrained Full-Chip Routing in Hierarchical Quad-Grid Model	顏金泰; YAN, JIN-TAI
中華大學	2006	Floorplan-Aware Decoupling Capacitance Budgeting on Equivalent Circuit Model	顏金泰; YAN, JIN-TAI
中華大學	2006	Area-Driven White Space Distribution for Detailed Floorplan Design	顏金泰; YAN, JIN-TAI
中華大學	2006	OPC-Aware Routing Reconstruction for OPE Reduction	顏金泰; YAN, JIN-TAI
中華大學	2006	Timing-Constrained Yield-Driven Wire Sizing for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2006	可避免干擾雜訊的SOC晶片繞線系統的開發	顏金泰
中華大學	2006	Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2005	Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Constrained Construction of Flexibility-Driven Routing Trees	顏金泰; YAN, JIN-TAI
中華大學	2005	Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Constrained Flexibility-Driven Routing Tree Construction	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points	顏金泰; YAN, JIN-TAI
中華大學	2005	Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids	顏金泰; YAN, JIN-TAI
中華大學	2005	Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation	顏金泰; YAN, JIN-TAI
中華大學	2005	Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model	顏金泰; YAN, JIN-TAI
中華大學	2005	Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Driven Steiner Tree Construction with Buffer Insertion	顏金泰; YAN, JIN-TAI
中華大學	2005	LB-Packing-Based Floorplan Design on DBL Representation	顏金泰; YAN, JIN-TAI
中華大學	2005	Floorplan-Aware Steiner Tree Reconstruction for Optimal Buffer Insertion	顏金泰; YAN, JIN-TAI
中華大學	2005	Optimal Shielding Insertion for Inductive Noise Avoidance	顏金泰; YAN, JIN-TAI
中華大學	2005	具有訊號完整性的SOC晶片電源供應系統設計	顏金泰
中華大學	2004	Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2004	Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization	顏金泰; YAN, JIN-TAI

Showing items 66-90 of 100 (4 Page(s) Totally)
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