臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

???ui.leftmenu.abouttair???
	???ui.leftmenu.explanation???

???ui.leftmenu.bartitle???
	Repositories
	Author
	Title
	Date
	???ui.leftmenu.statisticschart???
	???ui.leftmenu.realtimefacts???
	???ui.leftmenu.trend???

???index.news???
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

???ui.leftmenu.copyrighttitle???
	???ui.leftmenu.copyrightpublisher???
	???ui.leftmenu.copyrightconference???

???ui.leftmenu.link???
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"顏金泰"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1???	???jsp.browse.items-by-author.order2???

Showing items 71-95 of 100 (4 Page(s) Totally)
<< < 1 2 3 4 > >>
View [10|25|50] records per page

Institution	Date	Title	Author
中華大學	2006	OPC-Aware Routing Reconstruction for OPE Reduction	顏金泰; YAN, JIN-TAI
中華大學	2006	Timing-Constrained Yield-Driven Wire Sizing for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2006	可避免干擾雜訊的SOC晶片繞線系統的開發	顏金泰
中華大學	2006	Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2005	Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Constrained Construction of Flexibility-Driven Routing Trees	顏金泰; YAN, JIN-TAI
中華大學	2005	Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Constrained Flexibility-Driven Routing Tree Construction	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points	顏金泰; YAN, JIN-TAI
中華大學	2005	Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids	顏金泰; YAN, JIN-TAI
中華大學	2005	Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation	顏金泰; YAN, JIN-TAI
中華大學	2005	Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model	顏金泰; YAN, JIN-TAI
中華大學	2005	Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Driven Steiner Tree Construction with Buffer Insertion	顏金泰; YAN, JIN-TAI
中華大學	2005	LB-Packing-Based Floorplan Design on DBL Representation	顏金泰; YAN, JIN-TAI
中華大學	2005	Floorplan-Aware Steiner Tree Reconstruction for Optimal Buffer Insertion	顏金泰; YAN, JIN-TAI
中華大學	2005	Optimal Shielding Insertion for Inductive Noise Avoidance	顏金泰; YAN, JIN-TAI
中華大學	2005	具有訊號完整性的SOC晶片電源供應系統設計	顏金泰
中華大學	2004	Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2004	Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization	顏金泰; YAN, JIN-TAI
中華大學	2004	Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model	顏金泰; YAN, JIN-TAI
中華大學	2004	Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning	顏金泰; YAN, JIN-TAI
中華大學	2004	Double Bound List: A Dynamic Contour-Based Compacted Representation of Non-Slicing Floorplans on LB-Packing Solution Model	顏金泰; YAN, JIN-TAI
中華大學	2004	A Simulated-Annealing-Based Approach for Timing-Constrained Flexibility-Driven Routing Tree Construction	顏金泰; YAN, JIN-TAI
中華大學	2003	Optimal Wire Sizing for DME-Based Zero-Skew Clock Routing	顏金泰; YAN, JIN-TAI

Showing items 71-95 of 100 (4 Page(s) Totally)
<< < 1 2 3 4 > >>
View [10|25|50] records per page

	English \| 正體中文 \| 简体中文 \| 2831195
	???header.visitor??? : 33216207 ???header.onlineuser??? : 1117 ???header.sponsordeclaration???