臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T08:18:10Z	Effective Design-for-Testability Techniques for H.264 All-Binary Integer Motion Estimation	P. Y. Yeh;B. Y. Ye;S. Y. Kuo; P. Y. Yeh; B. Y. Ye; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T08:18:10Z	Effective Design-for-Testability Techniques for H.264 All-Binary Integer Motion Estimation	P. Y. Yeh;B. Y. Ye;S. Y. Kuo; P. Y. Yeh; B. Y. Ye; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T07:41:49Z	Scalable and bijective cells for C-testable iterative logic array architectures	SY-YEN KUO; I. Y. Chen; P. Y. Yeh; S. Y. Kuo; B. Y. Ye; B. Y. Ye;P. Y. Yeh;S. Y. Kuo;I. Y. Chen
臺大學術典藏	2018-09-10T07:41:49Z	Scalable and bijective cells for C-testable iterative logic array architectures	SY-YEN KUO; I. Y. Chen; P. Y. Yeh; S. Y. Kuo; B. Y. Ye; B. Y. Ye;P. Y. Yeh;S. Y. Kuo;I. Y. Chen
臺大學術典藏	2018-09-10T07:41:49Z	Design-for-Testability Techniques for Arithmetic Circuits	B. Y. Ye;P. Y. Yeh;S. Y. Kuo;I. Y. Chen; B. Y. Ye; P. Y. Yeh; S. Y. Kuo; I. Y. Chen; SY-YEN KUO
臺大學術典藏	2018-09-10T07:41:49Z	Design-for-Testability Techniques for Arithmetic Circuits	B. Y. Ye;P. Y. Yeh;S. Y. Kuo;I. Y. Chen; B. Y. Ye; P. Y. Yeh; S. Y. Kuo; I. Y. Chen; SY-YEN KUO
臺大學術典藏	2018-09-10T07:41:48Z	Design-for-Testability Techniques for CORDIC Design	B. Y. Ye;P. Y. Yeh;S. Y. Kuo;I. Y. Chen; B. Y. Ye; P. Y. Yeh; S. Y. Kuo; I. Y. Chen; SY-YEN KUO
臺大學術典藏	2018-09-10T07:41:48Z	Design-for-Testability Techniques for CORDIC Design	B. Y. Ye;P. Y. Yeh;S. Y. Kuo;I. Y. Chen; B. Y. Ye; P. Y. Yeh; S. Y. Kuo; I. Y. Chen; SY-YEN KUO

Showing items 1-8 of 8 (1 Page(s) Totally)
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