臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

	English \| 正體中文 \| 简体中文 \| Total items :2831143
	Visitors : 33144171 Online Users : 592 Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library

Scope

Adv. Search

Login

Administrator

臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

About TAIR
	About TAIR

Browse By
	Institution
	Author
	Title
	Date
	Statistics Chart
	Institution Facts
	Trend

News
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

Copyright
	Publisher & Journal Policy
	TAIR Copyright Conference Minutes

Related Links
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"c b hsu"

Return to Browse by Author
Sorting by Title	Sort by Date

Showing items 1-8 of 8 (1 Page(s) Totally)
1
View [10|25|50] records per page

Institution	Date	Title	Author
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC	G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC	G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO

Showing items 1-8 of 8 (1 Page(s) Totally)
1
View [10|25|50] records per page