臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
國立中山大學	1998-11	1 GHz 64-bit High-Speed Comparator Using ANT Dynamic Logic with Two-Phase Clocking	C.C. Wang;C.F. Wu;K.C. Tsai
國立中山大學	1998-06	Design of single-ended SRAM with high test coverage and short test time	C.F. Wu;C.C. Wang;R.T. Hwang;C.H. Kao
國立中山大學	1998-04	Design of fast dynamic CMOS comparators with fewer transistor count	C.F. Wu;C.C. Wang;Y.L. Tseng;C.H. Kao
國立中山大學	1997-12	A low-power and high-speed dynmaic PLA circuit configurationfor single-clock CMOS	C.C. Wang;C.F. Wu;R.T. Hwang;C.H. Kao
國立中山大學	1997-09	IDDQ testable configuration for PLAs by transformation into inverters	C.F. Wu;C.C. Wang;R.T. Hwang;C.H. Kao

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