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"chiu po yen"
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| 國立交通大學 |
2014-12-08T15:10:12Z |
ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process
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Hsiao, Yuan-Wen; Ker, Ming-Dou; Chiu, Po-Yen; Huang, Chun; Tseng, Yuh-Kuang |
| 義守大學 |
2009 |
Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process
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Chiu, Po-Yen ; Ker, Ming-Dou ; Tsai, Fu-Yi ; Chang, Yeong-Jar |
| 義守大學 |
2009 |
On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process
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Ker, Ming-Dou ; Chiu, Po-Yen ; Tsai, Fu-Yi ; Chang, Yeong-Jar |
Showing items 11-13 of 13 (1 Page(s) Totally)
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