|
English
|
正體中文
|
简体中文
|
總筆數 :0
|
|
造訪人次 :
52674813
線上人數 :
634
教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
|
|
|
"chou fang ting"的相關文件
顯示項目 1-8 / 8 (共1頁)
1
每頁顯示[10|25|50]項目
| 國立交通大學 |
2018-08-21T05:53:39Z |
Dual-output switched-capacitor DC-DC converter with pseudo-three-phase swap-and-cross control and amplitude modulation mechanism
|
Chen, Chia-Min; Su, Chung-Cheng; Chou, Fang-Ting; Hung, Chung-Chih |
| 國立交通大學 |
2017-04-21T06:56:16Z |
Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
|
Chou, Fang-Ting; Hung, Chung-Chih |
| 國立交通大學 |
2017-04-21T06:49:03Z |
A Novel 12-bit Current-Steering DAC with Two Reference Currents
|
Chou, Fang-Ting; Chen, Zong-Yi; Chu, Hsing-Chien; Hung, Chung-Chih |
| 國立交通大學 |
2015-12-02T03:00:57Z |
A Novel Glitch Reduction Circuitry for Binary-Weighted DAC
|
Chou, Fang-Ting; Chen, Chia-Min; Chen, Zong-Yi; Hung, Chung-Chih |
| 國立交通大學 |
2015-07-21T11:20:54Z |
A compact 12-bit DAC with novel bias scheme
|
Chou, Fang-Ting; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-12T02:44:30Z |
高性能之二進位式數位類比轉換器
|
周芳鼎; Chou, Fang-Ting; 洪崇智; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-08T15:35:50Z |
A low-glitch binary-weighted DAC with delay compensation scheme
|
Chou, Fang-Ting; Chen, Chia-Min; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-08T15:34:51Z |
Dual-Output Switched-Capacitor DC-DC Converter With Peseudo-Three-Phase Swap-and-Cross Control and Amplitude Modulation Mechanism
|
Chen, Chia-Min; Chiang, Chun-Yen; Du, Chen-Cheng; Chou, Fang-Ting; Hung, Chung-Chih |
顯示項目 1-8 / 8 (共1頁)
1
每頁顯示[10|25|50]項目
|
