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Showing items 1-9 of 9 (1 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T04:56:05Z |
A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design
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Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 國立臺灣大學 |
1993 |
An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digital Circuit Si[20642:0:4] 50300022:31:An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digit
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Chow, H. C.; 馮武雄; Kuo, J. B.; Chow, H. C.; Feng, Wu-Shiung; Kuo, J. B. |
| 國立臺灣大學 |
1992-09 |
An Improved Analytical Model for Short-Channel MOSFET's
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Chow, H. C.; 馮武雄; Chow, H. C.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1992-07 |
Simple analytical model for short-channel MOS devices
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Chow, H.-C.; Feng, W.-S.; Kuo, J.B. |
| 國立臺灣大學 |
1992-06 |
Model for propagation delay evaluation of CMOS inverter including input slope effects for timing verification
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Chow, H.C.; Feng, W.-S. |
| 國立臺灣大學 |
1992-02 |
Analytical delay model of CMOS inverter including channel-length modulation
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Chow, H.-C.; Feng, W.-S. |
| 國立臺灣大學 |
1992 |
An Analytical CMOS Inverter Delay Model Including Channel-Length Modulations
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Chow, H. C.; 馮武雄; Chow, H. C.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1992 |
A Short-Channel CMOS Inverter Propagation Delay Model Suitable for Timing Verification
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Chow, H. C.; 馮武雄; Chow, H. C.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1990 |
An Improved Analytical Model of Short Channel MOSFETs Suitable for Circuit Simulation
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Chow, H. C.; Wang, J. H.; Kuo, J, B.; 馮武雄; Chow, H. C.; Wang, J. H.; Kuo, J, B.; Feng, Wu-Shiung |
Showing items 1-9 of 9 (1 Page(s) Totally)
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