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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"dai chia tsen"的相關文件
顯示項目 1-10 / 10 (共1頁)
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| 國立交通大學 |
2018-08-21T05:54:21Z |
Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25-mu m 60-V/5-V BCD Technology
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2018-08-21T05:53:13Z |
Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:56:35Z |
Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:55:35Z |
ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:10Z |
ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-12T01:55:04Z |
高壓製程之靜電放電防護設計
|
戴嘉岑; Dai, Chia-Tsen; 柯明道; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:36:53Z |
Study on ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Applications
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:32:12Z |
Investigation on Safe Operating Area and ESD Robustness in a 60-V BCD Process with Different Deep P-Well Test Structures
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Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:30:45Z |
Self-Protected LDMOS Output Device with Embedded SCR to Improve ESD Robustness in 0.25-mu m 60-V BCD Process
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Huang, Yu-Ching; Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:28:41Z |
Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process
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Dai, Chia-Tsen; Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Peng, Yan-Hua; Tsai, Chia-Ku |
顯示項目 1-10 / 10 (共1頁)
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每頁顯示[10|25|50]項目
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