English  |  正體中文  |  简体中文  |  2831685  
???header.visitor??? :  33335117    ???header.onlineuser??? :  810
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

"donghyun baik"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1??? ???jsp.browse.items-by-author.order2???

Showing items 1-2 of 2  (1 Page(s) Totally)
1 
View [10|25|50] records per page

Institution Date Title Author
臺大學術典藏 2018-09-10T05:29:22Z False Path and Clock Scheduling Based Yield-Aware Gate Sizing Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:54Z A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN

Showing items 1-2 of 2  (1 Page(s) Totally)
1 
View [10|25|50] records per page