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Institution Date Title Author
臺大學術典藏 2018-09-10T05:29:22Z False Path and Clock Scheduling Based Yield-Aware Gate Sizing Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:54Z A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN

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