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Institution Date Title Author
國立交通大學 2014-12-08T15:27:55Z ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN SHEN, WZ; TAO, YH; DUNG, LR
國立交通大學 2014-12-08T15:26:30Z An automated IP synthesizer for limited-resource DWT processor Wei, TH; Huang, SR; Dung, LR
國立交通大學 2014-12-08T15:26:27Z VLSI implememtation for MAC-level DWT architecture Huang, SR; Dung, LR
國立交通大學 2014-12-08T15:26:16Z A novel vario-power architecture of motion estimation using a content-based subsample algorithm Cheng, HW; Dung, LR
國立交通大學 2014-12-08T15:26:14Z A content-based motion estimation algorithm for power-aware architecture Cheng, HW; Dung, LR; Yen, JH; Wang, JJ
國立交通大學 2014-12-08T15:25:38Z On improving dynamic range of wideband multistage Sigma Delta modulator using nonlinear oscillation Chang, TH; Dung, LR; Guo, JY
國立交通大學 2014-12-08T15:25:24Z Modeling and formal verification of dataflow graph in system-level design using Petri net Chiang, TH; Dung, LR; Yaung, MF
國立交通大學 2014-12-08T15:25:23Z Design of power-aware multiplier with graceful quality-power trade-offs Yen, JH; Dung, LR; Shen, CY
國立交通大學 2014-12-08T15:25:23Z On reducing leakage quantization noise of multistage Sigma Delta modulator using nonlinear oscillation Chang, TH; Dung, LR; Guo, JY
國立交通大學 2014-12-08T15:18:14Z A content-based methodology for power-aware motion estimation architecture Cheng, HW; Dung, LR

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