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Showing items 11-20 of 20 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:27:55Z |
ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN
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SHEN, WZ; TAO, YH; DUNG, LR |
| 國立交通大學 |
2014-12-08T15:26:30Z |
An automated IP synthesizer for limited-resource DWT processor
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Wei, TH; Huang, SR; Dung, LR |
| 國立交通大學 |
2014-12-08T15:26:27Z |
VLSI implememtation for MAC-level DWT architecture
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Huang, SR; Dung, LR |
| 國立交通大學 |
2014-12-08T15:26:16Z |
A novel vario-power architecture of motion estimation using a content-based subsample algorithm
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Cheng, HW; Dung, LR |
| 國立交通大學 |
2014-12-08T15:26:14Z |
A content-based motion estimation algorithm for power-aware architecture
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Cheng, HW; Dung, LR; Yen, JH; Wang, JJ |
| 國立交通大學 |
2014-12-08T15:25:38Z |
On improving dynamic range of wideband multistage Sigma Delta modulator using nonlinear oscillation
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Chang, TH; Dung, LR; Guo, JY |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Modeling and formal verification of dataflow graph in system-level design using Petri net
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Chiang, TH; Dung, LR; Yaung, MF |
| 國立交通大學 |
2014-12-08T15:25:23Z |
Design of power-aware multiplier with graceful quality-power trade-offs
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Yen, JH; Dung, LR; Shen, CY |
| 國立交通大學 |
2014-12-08T15:25:23Z |
On reducing leakage quantization noise of multistage Sigma Delta modulator using nonlinear oscillation
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Chang, TH; Dung, LR; Guo, JY |
| 國立交通大學 |
2014-12-08T15:18:14Z |
A content-based methodology for power-aware motion estimation architecture
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Cheng, HW; Dung, LR |
Showing items 11-20 of 20 (1 Page(s) Totally)
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