English  |  正體中文  |  简体中文  |  Total items :0  
Visitors :  50716732    Online Users :  406
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
About TAIR

Browse By

News

Copyright

Related Links

"f wang"

Return to Browse by Author
Sorting by Title Sort by Date

Showing items 16-27 of 27  (1 Page(s) Totally)
1 
View [10|25|50] records per page

Institution Date Title Author
臺大學術典藏 2018-09-10T04:35:38Z Verification of Embedded Systems with BDD-like Data-Structures F. Wang; FARN WANG
臺大學術典藏 2018-09-10T04:35:38Z TCTL Inevitability Analysis of Dense-Time Systems F. Wang; G.-D. Hwang; F. Yu; FARN WANG
臺大學術典藏 2018-09-10T04:35:37Z Real-Time Distributed System Specification and Verification in APTL F. Wang;A.K. Mok;E.A. Emerson; F. Wang; A.K. Mok; E.A. Emerson; FARN WANG
臺大學術典藏 2018-09-10T04:35:37Z Efficient Verification of Timed Automata with BDD-like Data-Structures F. Wang,; FARN WANG
臺大學術典藏 2018-09-10T04:15:26Z Efficient and User-Friendly Verification. F. Wang; P.-A. Hsiung; FARN WANG
臺大學術典藏 2018-09-10T04:15:26Z Symmetric Model-Checking of Concurrent Timed Automata with Clock-Restriction Diagram F. Wang; FARN WANG
臺大學術典藏 2018-09-10T04:15:26Z Symmetric Symbolic Safety-Analysis of Concurrent Software with Pointer Data Structures F. Wang; K. Schmidt; FARN WANG
臺大學術典藏 2018-09-10T03:50:34Z Parametric Optimization of Open Real-Time Systems F. Wang; H.-C. Yen; FARN WANG
臺大學術典藏 2018-09-10T03:50:34Z RED: Model-Checker for Timed Automata with Clock-Restriction Diagram F. Wang; FARN WANG
臺大學術典藏 2018-09-10T03:50:34Z Symbolic Verification of Complex Real-Time Systems with Clock-Restriction Diagram F. Wang; FARN WANG
中原大學 2005 PLS Based dEWMA Controller for MIMO Non-Squared Semiconductor J. Chen;F. Wang;
中原大學 2004 PLS Based Run-to-Run Control Design for MIMO Non-Squared Semiconductor Processes F. Wang;J. H.Chen;

Showing items 16-27 of 27  (1 Page(s) Totally)
1 
View [10|25|50] records per page