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Showing items 11-20 of 59  (6 Page(s) Totally)
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Institution Date Title Author
國立交通大學 2015-12-02T03:00:54Z Stability/Performance Assessment of Monolithic 3D 6T/ST SRAM Cells Considering Transistor-Level Interlayer Coupling Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T11:21:14Z Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T11:20:55Z Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:31:27Z Evaluation of Read-and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:31:16Z Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:31:11Z Evaluation of Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM Cells Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:29:06Z Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation Lee, Ko-Chun; Fan, Ming-Long; Su, Pin
國立交通大學 2015-07-21T08:29:05Z Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET Fan, Ming-Long; Hu, Vita Pi-Ho; Hsu, Chih-Wei; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:28:07Z Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-16T06:15:18Z SCHMITT TRIGGER-BASED FINFET SRAM CELL Chuang Ching-Te; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin

Showing items 11-20 of 59  (6 Page(s) Totally)
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